The JTAG connections on the SoC are wired directly to the JTAG Header J5 on the SYZYGY Hub to facilitate SoC debugging, FPGA configuration, and ChipScope usage using a Xilinx JTAG cable. The JTAG interface presented at MC2 is a 3.3V interface corresponding to the FPGA JTAG I/O voltage. The 2mm connector provided on the hub is a Xilinx standard and is compatible with the Xilinx Platform Cable USB. A JTAG connection between the PS and PL portions of the SoC is made internally on the Zynq, so a single JTAG connection can support both.