DDR3 Memory

The DDR3 SDRAM is connected exclusively to the dedicated PS memory controller on Bank 502 of the SoC.

MIG Settings

Zynq 7000 devices support external, high-performance memory through the use of the hard PS memory controller on the SoC. This controller configuration is handled using the ZYNQ7 Processing System IP. At boot, the controller is configured by the FSBL or U-Boot SPL. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on the ZYNQ7 Processing System IP version 5.5 and Vivado 2017.2.

DDR Controller Configuration
Memory TypeDDR3 SDRAM
Memory PartMT41K256M16 RE-125
Effective DRAM Bus Width32 Bit
Burst Length8
Internal VrefDisabled
Junction Temperature (C)Normal (0-85)
Memory Part Configuration
DRAM IC Bus Width16 Bits
DRAM Device Capacity4096 MBits
Speed BinDDR3_1066FF
All othersDefault
Training/Board Details (User Input)
Write levelingEnabled
Read gateEnabled
Read data eyeEnabled
All DQS to Clock Delay (ns)0.0
All Board Delay (ns)0.25
Additive Latency (ns)0
Enable Advanced optionsDisabled