ZYNQ7 Processing System
The hard processor system (PS) on the Zynq 7 requires configuration to understand how to interact with the peripherals on the Brain-1. At boot, this configuration is entered into registers on the CPU through the FSBL or U-Boot SPL. Any changes made to this configuration will require generating a new hardware handoff (hdf) file along with a re-build of the U-Boot SPL or FSBL.
The configuration parameters below correspond to the configuration for the reference design provided by Opal Kelly. Applications conforming to the settings outlined below will be compatible with the reference designs and official Linux image from Opal Kelly. Other designs may require some changes to the parameters listed below, resulting in incompatibilities with the Opal Kelly U-Boot and Linux configuration.
PS-PL Configuration
| PARAMETER | SYZYGY BRAIN-1 |
|---|---|
| General | |
| UART0 Baud Rate | 115200 |
| UART1 Baud Rate | N/A |
| Enable Clock Resets->FCLK_RESET0_N | Enabled |
| Other settings | Default/Disabled |
| AXI Non Secure Enablement | 0 |
| M AXI GP0 interface | Enabled |
| HP Slave AXI Interface | |
| S AXI HP0 interface | Enabled |
| S AXI HP0 DATA WIDTH | 64 |
| All other settings | Default/Disabled |
Peripheral I/O Pins
| MIO PIN (RANGE) | ASSIGNMENT |
|---|---|
| 0-11 | GPIO MIO |
| 12-13 | I2C1 |
| 14-15 | UART0 |
| 16-27 | Enet0 |
| 28-39 | USB0 |
| 40-45 | SD0 |
| 46 | SD0 Card Detect |
| 47 | USB PHY Reset |
| 48-50 | GPIO MIO |
| 51 | Ethernet PHY Reset |
| 52-53 | Ethernet 0 MDIO |
| EMIO | I2C0 |
MIO Configuration
This majority of this section is configured correctly according to the settings entered in the Peripheral I/O Pins section.
Bank 0 on the Brain-1 runs at 3.3V (LVCMOS 3.3V), while Bank 1 runs at 1.8V (LVCMOS 1.8V).
The following changes should be made:
| I/O PERIPHERALS | |
|---|---|
| SD 0 | |
| CD | MIO 46 |
| GPIO | |
| ENET Reset | Share reset pin |
| ENET0 Reset | MIO 51 |
| USB Reset | Share reset pin |
| USB0 Reset | MIO 47 |
| I2C Reset | Share reset pin |
Clock Configuration
The PS receives a 50 MHz input clock. The reference design configures the CPU Clock Ratio to 6:2:1.
| COMPONENT | CLOCK SOURCE | REQUESTED FREQUENCY (MHZ) |
|---|---|---|
| Processor/Memory Clocks | ||
| CPU | ARM PLL | 666.666 |
| DDR | DDR PLL | 533.333 |
| IO Peripheral Clocks | ||
| ENET0 | IO PLL | 1000 Mbps |
| SDIO | IO PLL | 100 |
| PL Fabric Clocks | ||
| FCLK_CLK0 | IO PLL | 125 |
| FCLK_CLK1 | IO PLL | 40 |
| FCLK_CLK2 | IO PLL | 24 |
| FCLK_CLK3 | IO PLL | 200 |
DDR Configuration
(see the DDR3 Memory page)
Interrupts
All Fabric Interrupts are disabled by default in the reference design.