The Micron DDR3 SDRAM is connected exclusively to the 1.5-v I/O on Banks 15 and 16 of the FPGA. The tables below list these connections.

The following resources are available to help provide guidance for designs that involve this memory:

• How-To Apply DDR MIG Settings and Vivado Board File to generate Xilinx’s MIG IP Core.
• The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
• The XEM7310MT Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

Artix-7 devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on MIG 4.0 and Vivado 2016.2.