DDR3 Memory

The Micron DDR3 SDRAM is connected exclusively to the I/O on Bank 35 of the FPGA. The tables below list these connections.

The following resources are available to help provide guidance for designs that involve this memory:

  • The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
  • The XEM7305 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

Connection Tables

DDR3 PINFPGA PIN
RESETF1
CKpC5
CKnB5
CKEC3
RASE6
CASB7
WED5
DQS0pF3
DQS0nE3
DQS1pG2
DQS1nG1
DM0D1
DM1H3
ODTA7
DDR3 PINFPGA PIN
A0A5
A1B3
A2A6
A3D7
A4B2
A5C7
A6C4
A7A8
A8C2
A9A4
A10B4
A11B1
A12A3
A13E5
A14C1
BA0F6
BA1A2
BA2D6
DDR3 PINFPGA PIN
D0F4
D1F2
D2G5
D3E1
D4E4
D5D2
D6F5
D7E2
D8H2
D9H4
D10J1
D11H6
D12J3
D13J4
D14J2
D15H5

MIG Settings

Spartan-7 devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by Xilinx. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on MIG 4.2 and Vivado 2017.3.

PARAMETERXEM7305
Controller TypeDDR3 SDRAM
Clock Period3076ps (325.00MHz)
PHY to Controller Clock Ratio4:1
Memory TypeComponents
Memory PartMT41K256M16XX-125
Memory Voltage1.5V
Data Width16
ECCDisabled
Data MaskEnabled
OrderingNormal
Input Clock Period4998ps (200.08MHz)
Read Burst Type and LengthSequential
Output Driver Impedance ControlRZQ/7
Controller Chip Select PinDisable
RTT (nominal) – On Die Termination (ODT)RZQ/6
Memory Address MappingBANK | ROW | COLUMN
System ClockDifferential
Reference ClockUse System Clock
System Reset PolarityActive High
Debug Signals for Memory ControllerOff
Internal VrefEnabled
IO Power ReductionOn
XADC InstantiationEnabled
Internal Termination Impedance60 Ohms
sys_clk_p/n Bank Number34
sys_clk_p/n Pin NumberR2/R1(CC_P/N)
Rtt WR – Dynamic ODTDynamic ODT off
DIFF_TERM_SYSCLKFALSE