Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.
Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.
The Pins reference for the XEM7305 may be found at the link to the right.
Two high-density, 80-pin expansion connectors are available on the top side of the XEM7305 PCB. These expansion connectors provide user access to several power rails on the XEM7305, the JTAG interface on the FPGA, and 108 I/O pins on the FPGA, including several MRCC clock inputs.
The connectors on the XEM7305 are Samtec part number: BSE-040-01-F-D-A. The table below lists the appropriate Samtec mating connectors along with the total mated height.
|SAMTEC PART NUMBER||MATED HEIGHT|
MC1 contains most of the system power supply pins in addition to 48 FPGA I/O connections. Please see the XEM7305 Pins Reference for details.
- +5VUSB from the USB connector
- +3.3VDD, +1.5VDD, +1.8VDD, and +1.0VDD system supplies
MC2 contains the JTAG pins, some I/O power supply pins, and 46 FPGA I/O connections.
- JTAG TCK, TMS, TDI, TDO
- XADC VP, VN
|FPGA BANK||PINS ON MC1||PINS ON MC2||TOTAL||POWER SUPPLIES|
|Bank 15||50||0||50||VCCO_MC1 (MC1-12, 13)|
|Bank 34||0||48||48||VCCO_MC2 (MC2-41, 42)|
|Bank 16||0||10||10||VCCO_MC2 (MC2-41, 42)|
The Xilinx Spartan 7 design establishes several pins that offer dedicated access to the on-chip clock PLL inputs and outputs. These pins are shared with I/O and other functionality, but may have some limitations or restrictions. Please review Xilinx’s Spartan 7 documentation to understand how these limitations may affect your design.
|FPGA BANK||FPGA PINS||MCX PINS|
Considerations for Differential Signals
The XEM7305 PCB layout and routing has been designed with several applications in mind but, due primarily to space limitations, pair routing has not been performed. The board should still operate over a broad range of frequencies for differential standards, but may require some length matching on the peripheral for best performance. Routed lengths on the XEM7305 PCB for routes to the expansion connector are listed in the Pins reference.
The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.
I/O Voltage Pins (VCCIO and Vref)
Please see the section Powering the XEM7305 for details on providing the necessary power for the I/O banks.
I/O State at Power On
Xilinx Artix-7 FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the XEM7305 holds the PUDC_B pin high with a 1kΩ resistor at R25, disabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 0Ω resistor at R27 and removing the 1kΩ resistor at R25, forcing the PUDC_B pin to ground.