SmartVIO is SYZYGY’s mechanism for automatically negotiating and supplying the correct I/O voltage to connected peripherals. Each SYZYGY peripheral stores a DNA record — a small data structure that describes the peripheral’s electrical requirements, including the range of I/O voltages it can accept. When a carrier powers up, its SmartVIO controller reads the DNA from every connected peripheral over I2C, computes the intersection of their acceptable voltage ranges, and configures a programmable voltage regulator to supply the agreed-upon VIO voltage. This process happens automatically, without any involvement from the FPGA or host PC.

• Full SYZYGY compliance — SmartVIO is what makes a carrier truly SYZYGY-compliant. Without it, you have the connector, but not the ecosystem.
• Low design effort — Reference schematics, suggested part numbers, and sample firmware are provided, so most of the work is already done.
• Broad peripheral compatibility — A fixed VIO locks your carrier to one voltage; SmartVIO works with any compliant peripheral, regardless of what voltage it requires.
• Eliminates user error — Manual VIO adjustment invites misconfiguration and damaged hardware. SmartVIO makes the right voltage automatic and guaranteed.
• Minimal BOM impact — The added components — an adjustable regulator, a small MCU, and supporting passives — are inexpensive and widely available.

Without SmartVIO, the carrier designer or system integrator must know in advance which peripherals will be used and hard-wire the I/O voltage accordingly. This works for a fixed design, but breaks down when the carrier is intended to be general-purpose or when a user connects an unexpected peripheral. A mismatch between the peripheral’s required logic voltage and the carrier’s I/O supply can damage hardware on the carrier or peripheral.

SmartVIO eliminates this risk. A carrier that implements SmartVIO is compatible with any SYZYGY-compliant peripheral, past or future, without requiring any carrier-side changes. It also enables mixed-voltage systems: peripherals with different VIO requirements can coexist on the same carrier by placing them in separate VIO groups, each independently regulated.

Implementing SmartVIO is straightforward: Opal Kelly provides reference source code for both the peripheral MCU and the SmartVIO controller, along with hardware examples and specific IC recommendations. The sections that follow describe each component in detail and show how to adapt the reference materials to your design.

Figure 1: SmartVIO Block Diagram

The SmartVIO controller is the component on the carrier responsible for reading peripheral DNA, negotiating VIO voltages, and enabling the appropriate power rails. It can be implemented in one of several ways: as a dedicated microcontroller, as part of a larger system MCU that also handles other carrier functions, as a soft-core processor within the FPGA, or as a software process running on an embedded processor such as the ARM cores in a Zynq SoC. An MCU-based implementation is more typical and is the focus of this section.

At power-up, the SmartVIO controller performs the following sequence:

1. Wait for 3.3V supply. Wait at least 100 ms after the 3.3V supply has stabilized. This ensures that all connected pods are powered and their pMCUs are ready to respond to I2C queries.
2. Read pod DNA. Enumerate all SYZYGY ports over I2C and read the DNA record from each pod’s pMCU.
3. Verify CRC. Verify the CRC-16 of each DNA record. Discard records that fail validation.
4. Parse DNA records. Extract VIO voltage ranges, current consumption data, and attribute flags from each DNA record.
5. Run VIO solver. For each VIO group, the VIO solver computes the intersection of the acceptable voltage ranges across all connected pods in that group.
6. Configure VIO supply. If a valid intersection exists, set the VIO regulator to the lowest voltage of that range and enable the supply. If no valid intersection exists — for example, due to incompatible pods — leave VIO disabled for that group.

The syzygy-tools library provides a portable C implementation of this sequence that carrier designers can integrate directly — to even very simple, very low cost MCUs.

The Brain-1 carrier provides an example using the ARM cores in a Zynq SoC. In this design, SmartVIO runs as a Linux application.

The VIO solver is the algorithm that determines the correct VIO voltage for each group of SYZYGY ports. Each peripheral’s DNA record includes up to four acceptable VIO voltage ranges, specified in 10 mV steps. The solver finds the intersection of at least one range from each pod in a group. If an overlap exists across all pods, VIO is set to the midpoint of the resulting range. If no overlap exists, VIO remains disabled for that group.

The solver also handles error conditions: CRC failures, DNA version mismatches, and port type mismatches all result in VIO being kept disabled for the affected group. The syzygy-tools repository includes a test suite (smartvio-test) that validates the solver against a set of known cases, which can be useful during development and integration.

The memory requirements for a SmartVIO controller are modest. At a minimum, the controller must be able to hold the 40-byte DNA header for each connected peripheral simultaneously, along with working variables for the solver. Full DNA payloads can be up to approximately 256 bytes per peripheral.

In practice, the ATmega328P — a widely available part less than $2 — is more than adequate, providing 32 KB of flash and 2 KB of SRAM with room to spare for additional carrier functions. Smaller and less expensive parts may be sufficient for designs that only require SmartVIO functionality.

The SmartVIO controller acts as the I2C master for all SYZYGY ports on the carrier. The SYZYGY I2C bus operates at 3.3V logic. If the controller MCU operates at a different voltage, a bidirectional level translator such as the TI PCA9306 is required. Pull-up resistors for SDA and SCL must be provided on the carrier.

If the carrier MCU shares an I2C bus with other devices, it is worth considering giving SYZYGY its own dedicated bus. This avoids potential address collisions and prevents the SmartVIO enumeration process from inadvertently accessing non-SYZYGY devices.

MCU I2C implementations vary. Some provide a dedicated hardware I2C peripheral. Others implement two-wire communication via a Universal Serial Interface (USI) in TWI mode, as in the ATtiny44A used in the reference pMCU firmware. Bit-banged implementations are also possible. Each approach has trade-offs in complexity, timing accuracy, and CPU overhead.

Some programmable voltage regulators use PMBus for communication. PMBus is a power management protocol derived from SMBus (System Management Bus), which is itself a subset of I2C with additional electrical and timing constraints. PMBus adds a standardized command language on top of SMBus, and some regulators may require PMBus-compliant communication rather than plain I2C. If the chosen voltage regulator has PMBus requirements, the controller’s I2C implementation must be compatible — this is worth confirming early in component selection.

Beyond I2C, the SmartVIO controller may need GPIO connections to the VIO voltage regulator. Enable outputs and power-good inputs are common examples, though the exact interface varies by part. See the Power Distribution System section for more detail on regulator selection and interface requirements.

Every SYZYGY peripheral must include a microcontroller — the peripheral MCU, or pMCU — that serves as an I2C slave on the SYZYGY bus. Its primary function is to store and serve the peripheral’s DNA record, which the SmartVIO controller reads at startup to negotiate VIO voltage. Optionally, the pMCU can also manage power supply sequencing on the peripheral, controlling the order in which power rails are enabled.

Opal Kelly provides reference firmware for the ATtiny44A (avr-dna-fw), a small, inexpensive AVR microcontroller well-suited to this role. The sections below describe requirements and recommendations based on this reference implementation.

The pMCU requires three types of memory, each serving a distinct purpose:

Flash stores both the firmware and the DNA record. On the ATtiny44A, the 4 KB flash is partitioned into 3 KB for firmware and 1 KB reserved for DNA. DNA is written to flash using AVR self-programming rather than stored in EEPROM, because DNA can occupy up to 1 KB — larger than the available EEPROM on small AVR parts. Self-programming requires the SELFPRGEN fuse to be enabled; this is easy to overlook and will prevent DNA from being written if not set correctly.

EEPROM stores configuration data such as power sequencer settings. Using EEPROM for this purpose keeps the configuration separate from the firmware image, allowing sequencer parameters to be written or adjusted independently during development and production without requiring a full firmware reflash. Once finalized for a given design, these settings are written during production and are unlikely to change thereafter.

SRAM is used for I2C buffers and working variables. 256 bytes is sufficient for the reference implementation.

The following pins are required on any pMCU implementation:

• I2C (SDA, SCL) — The pMCU operates as an I2C slave on the SYZYGY bus. These two pins are the only strictly required I/O for a minimal SmartVIO-compliant implementation.
• R_GA ADC input — A single ADC input reads the voltage on the R_GA line, which is set by a resistor divider between a carrier-provided pull-down and a pod-side pull-up. This voltage determines the pMCU’s I2C address, allowing multiple pods to share a common bus.

The following pins are optional, required only if the peripheral implements power supply sequencing:

• Supply voltage monitoring ADC inputs — Up to three ADC inputs can be used to monitor any of the supply rail voltages (VIO, 3.3V, and 5V, for example). The sequencer uses these to detect when each rail has reached a stable level before asserting the corresponding enable output.
• Sequencer enable outputs — Digital outputs used to gate power to peripheral circuitry in a defined sequence. The reference firmware supports three enable outputs, which is sufficient for most applications. Designers may choose to implement more or fewer depending on their peripheral’s requirements.

Additional optional pins:

• Programming header — An in-system programming (ISP) interface for loading firmware and DNA. The ATtiny44A uses a 4-pin SPI interface (SCK, MOSI, MISO, RESET), with SCK and MOSI shared with the I2C pins. Opal Kelly uses Tag-Connect footprints for programming headers, which eliminate the need for a connector body and save board space.
• Test mode pins — Pins reserved for production test functionality, used to verify pod connectivity and operation when connected to a carrier or test platform. Whether to include these is left to the designer’s discretion.

The carrier is responsible for generating and distributing three power rails to connected pods: 5V, 3.3V, and the adjustable VIO supply. This section covers regulator selection and requirements for each rail, considerations for pod-side local supplies, and general design considerations for a robust power distribution system.

The 3.3V and 5V rails are fixed supplies provided to all peripherals on the carrier. The SYZYGY specification requires the following power-up sequence:

1. Enable 5V supply.
2. Enable 3.3V supply — simultaneously with 5V or any time after.
3. Wait for 3.3V stabilization. The SmartVIO controller monitors the 3.3V regulator’s power-good output to determine when the supply has stabilized, then waits at least 100 ms before querying pods.
4. Enable VIO supply — only after all pods have been queried and the VIO voltage has been determined. See Controller Operation for details.

Both rails are shared across all pods on the carrier. As with VIO, the specification allows up to 2A per port per rail, though in practice most peripherals draw significantly less. Size regulators for the realistic combined load of all connected pods. Voltage tolerances per the SYZYGY specification are ±5% for 3.3V and ±10% for 5V.

The VIO rail is the adjustable I/O supply negotiated by the SmartVIO controller. The SYZYGY specification allows one to four (non-overlapping) voltage ranges, specified on 10 mV intervals. The minimum and maximum values of a range can be the same, allowing a series of discrete voltages. While not strictly required, it’s recommended that carriers support a VIO range of at least 1.2V to 3.3V for broadest peripheral compatibility.

Three types of adjustable regulators are suitable for SmartVIO implementation:

1. I2C/PMBus controllable regulators
2. Voltage selectable regulators
3. Feedback-controlled regulators

These regulators have a built-in digital interface, allowing the SmartVIO controller to set the output voltage directly over I2C or PMBus. They typically support fine voltage steps (10 mV or better), giving the VIO solver maximum flexibility. Examples include TI TPS65400, MPS MPM54304, and Microchip MIC24045.

If the VIO regulator shares an I2C bus with the SYZYGY pods, take care to avoid address conflicts. Placing the regulator on a separate bus provides a cleaner separation between the SmartVIO enumeration bus and the power management bus.

Multi-output regulators such as the MPM54304 (four outputs) are worth considering for carriers with multiple VIO groups, as they can simplify layout and reduce component count.

This type of regulator includes a set of digital input pins for selecting the output voltage from a predefined set of common voltages. Examples include Enpirion (Altera) EN5311 and Semtech SC183C.

Standard adjustable regulators can also be used by dynamically modifying the feedback divider to set the output voltage. Three circuit approaches are common:

• DAC — A DAC injects a current or voltage into the feedback node, shifting the output voltage.
• Digital potentiometer — A digitally controlled potentiometer (e.g., Microchip MCP4xxx series, controlled via I2C or SPI) replaces one resistor in the feedback divider, allowing the output voltage to be stepped programmatically.
• PWM filtered to DC — A PWM output from the SmartVIO controller MCU, filtered through an RC network, produces a control voltage on the feedback node. This avoids the need for a dedicated DAC or digital potentiometer IC, at the cost of additional filter design and potential output ripple if the filter is not well-designed.

Each approach involves trade-offs in cost, circuit complexity, noise performance, and achievable resolution. For detailed design guidance covering these techniques, see the TI application report SLVA861 and this Analog Devices technical article.

The VIO rail is shared among all pods within a VIO group. The SYZYGY specification allows up to 2A per port, limited by the Samtec connector pin rating. In practice, most peripherals draw well under this limit — many draw only tens to hundreds of milliamps on the VIO rail — so most carrier designers will not need to size regulators for worst-case simultaneous draw on every port. That said, it is good practice to account for the combined realistic load of all pods in a group when selecting a regulator.

If using SYZYGY cables rather than direct board-to-board connections, note that current capacity is reduced — see Cable Derating below.

Peripheral designers may wish to include locally generated supplies on the pod. A common example is a low-noise LDO regulator for noise-sensitive circuits such as ADCs and DACs, powered from the carrier-supplied 3.3V or 5V rail. If a local supply must be sequenced relative to VIO or other rails, the pMCU’s sequencer outputs can be used for this purpose — see the Peripheral MCU section for details.

• Soft-start — An adjustable soft-start on the VIO regulator limits inrush current when the supply is enabled.
• Cable derating — When pods are connected via SYZYGY cables rather than direct board-to-board mating, the current capacity per pin is reduced: 500 mA/pin for standard EQCD cables and 400 mA/pin for HQDP transceiver cables. Factor this into power budgeting for cable-connected systems.
• Overvoltage protection (OVP) — Consider OVP on the VIO rail to protect peripherals in the event of a regulator fault. This is especially important given the range of VIO voltages that may be in use across different peripherals.
• ESD protection — Apply appropriate ESD protection on supply pins, particularly at connectors.
• Thermal protection — Ensure adequate thermal design for the VIO regulator, particularly in high-current applications or dense board layouts. Regulators with built-in thermal shutdown provide a useful safety net.

SmartVIO negotiation happens at power-on; hot-plugging is not supported. VIO negotiation runs once, as part of the carrier’s power-up sequence, based on the peripherals present when the controller enumerates the bus. The reference controller does not re-run the solver or re-enumerate after startup, so peripherals are expected to be connected before the carrier is powered on.

Inserting or removing a peripheral on a powered carrier can apply a VIO voltage that was negotiated for a different set of peripherals — potentially outside the newly connected peripheral’s acceptable range — which may damage the peripheral or the carrier. Live insertion also bypasses the specified 5V → 3.3V → VIO power-up sequence, and the SYZYGY connectors are not designed for hot insertion.