Power
The devices on the FOMD-ACV require several power supplies to operate. Some are provided externally through the edge card. Some are derived internally using on-board power supplies.
External power rail connection pins can be found in the FOMD-ACV-A4 Pins Reference.
Input Supply Power
The FOMD-ACV must be provided a clean and well-regulated 2.8V to 5.5V source supplied to the edge connector.
On-board Regulators
| SUPPLY RAIL | VOLTAGE | TOLERANCE | SOURCE | NOTES / DEVICES |
|---|---|---|---|---|
| +2.5VDD | +2.5v | ± 5% | On-board switcher | FPGA PLL / Vccaux supplies |
| +1.35VDD | +1.35 | ± 5% | On-board switcher | DDR3 memory and FPGA I/O |
| +1.1VDD | +1.1 | ± 0.03v | On-board switcher | FPGA core |
I/O Triples
For each Altera FPGA I/O bank, there are three relevant power supplies. We call these three supplies an I/O Triple. These triples are set according to the I/O standard(s) required for I/O on the bank. Please refer to the extensive Altera documentation for more information on which settings are required for each standard. This power rails are supplied to the FOMD-ACV by the carrier board for the specific application.
- VCCIO – The I/O supply and is set according to the I/O standard selected for the bank.
- VCCPD – The pre-driver voltage for the bank. It is set according to:
- If VCCIO = 3.3v, set VCCPD = 3.3v
- If VCCIO = 3.0v, set VCCPD = 3.0v
- If VCCIO ≤ 2.5v, set VCCPD = 2.5v
- VREF – This is a reference voltage required for some standards. Note that this is not required for many of the supported I/O standards.
Bank Connections
Two I/O rails (each with a corresponding I/O Triple) and the programming rail must be provided by the FOMD-ACV carrier. Several I/O banks on the FPGA are shared among a single I/O supply. These power rail connections are listed in the tables below.
| FOMD SUPPLY PIN | FPGA BANKS | FPGA PINS | NOTES |
|---|---|---|---|
| VCCIO1 | 2A, 3A, 5A, 5B | VCCIO2A VCCIO3A VCCIO5A VCCIO5B | Valid voltages: 1.2V, 1.25V, 1.35V, 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V See Altera Cyclone V documentation for details. |
| VCCPD1 | 1A, 2A, 3A, 5A, 5B | VCCPD1A2A VCCPD3A VCCPD5A VCCPD5B | Pre-driver supply for associated banks. 2.5V, 3.0V, or 3.3V allowed |
| VREF1 | 2A, 3A, 5A, 5B | VREFB2AN0 VREFB3AN0 VREFB5AN0 VREFB5BN0 |
| FOMD SUPPLY PIN | FPGA BANKS | FPGA PINS | NOTES |
|---|---|---|---|
| VCCIO2 | 3B, 4A | VCCIO3B VCCIO4A | Valid voltages: 1.2V, 1.25V, 1.35V, 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V See Altera Cyclone V documentation for details. |
| VCCPD2 | 3B, 4A | VCCPD3B4A | Pre-driver supply for associated banks. 2.5V, 3.0V, or 3.3V allowed |
| VREF2 | 3B, 4A | VREFB2AN0 VREFB3AN0 |
| FOMD SUPPLY PIN | FPGA BANKS | FPGA PINS | NOTES |
|---|---|---|---|
| VCCPGM | N/A | VCCPGM | Programming bank voltages: 1.8V, 2.5V, 3.0V, or 3.3V For Active Serial, only 3.3V is allowed. |
VCCBAT
The VCCBAT rail is connected to the FPGAs VCCBAT pin. It is used for FPGA volatile storage and must be supplied by 1.2V to 3.0V. By default this rail is connected to the on-board 2.5V regulator by R1. If an external voltage source is desired, R1 must be removed and the source connected to the VCCBAT pin of the edge connector.