FPGA Configuration

Configuration Overview

All pins necessary for FPGA configuration are pinned out to the edge connector EC1. These pins and a brief description of their function are listed below. Please refer to the Altera Cyclone V documentation for more detail. Please refer to the FOMD-ACV Pins Reference for the edge connector pinout.

MSEL[4:0]Mode select
DCLKConfiguration clock input
CONF_DONEDriven by the FPGA when configuration completes
nCONFIGClears and initiates configuration
nSTATUSConfiguration status indicator
DATA[3:0]Configuration data for PS, AS x1, and AS x4 schemes
DATA[4] / nCSOConfiguration data for FPP scheme
Chip select (output) for AS scheme 
DATA[15:5]Configuration data for FPP x8 and FPP x16 schemes

Supported Configuration Modes

Passive SerialYesAll feature variations supported.
Active Serial (x1 and x4)YesAll feature variations supported.
JTAGYesAll feature variations supported.
FPP x8Yes (*)All feature variations supported.
FPP x16Yes (*)All feature variations supported.

* – See the section below on “Disconnecting the Configuration Flash” when using these programming modes.

On-Board Configuration Flash

A 128-Mbit, 3.3 V, 108 MHz SPI flash is available on the FOMD-ACV. This Flash can be used to configure the FPGA using the Active Serial (x1 or x4) configuration scheme. If this is used, VCCPGM must be 3.3 V. When running at lower voltages the SPI flash must be replaced with a 1.8 V compatible component or disconnected from the system (refer to “Disconnecting the Configuration Flash” below).

The on-board configuration flash can be programmed over JTAG using the instructions in the SPI Flash page.

Disconnecting the Configuration Flash

When using FPP x8, FPP x16 configuration modes, or when running VCCPGM at less than 3.3 V it is recommended to disconnect the SPI Flash from the FPGA entirely. This is made possible through a set of resistors that, when removed, will disconnect each pin of the SPI flash from the rest of the circuit with the exception of ground: