Expansion Connectors
Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.
Pins can also generate constraint files (QSF, SDC) and help you map your HDL net names to FPGA pin locations automatically.
The Pins reference for the ZEM5305 may be found at the link to the right.
Connector Details
Two high-density, 80-pin expansion connectors are available on the top side of the ZEM5305 PCB. These expansion connectors provide user access to several power rails on the board, the JTAG interface on the FPGA, and 94 I/O pins on the FPGA, including several dedicated clock inputs.
The connectors on the ZEM5305 are Samtec part number: BSE-040-01-F-D-A. The table below lists the appropriate Samtec mating connectors along with the total mated height.
| SAMTEC PART NUMBER | MATED HEIGHT |
|---|---|
| BTE-040-01-F-D-A | 5.00mm (0.197”) |
| BTE-040-02-F-D-A | 8.00mm (0.315”) |
| BTE-040-03-F-D-A | 11.00mm (0.433”) |
| BTE-040-04-F-D-A | 16.10mm (0.634”) |
| BTE-040-05-F-D-A | 19.10mm (0.752”) |
FPGA Connections
MC1 contains most of the system power supply pins in addition to 48 FPGA I/O connections. Please see the ZEM5305 Pins Reference for details.
- +5VUSB from the USB connector
- +3.3VDD, +2.5VDD, +1.5VDD, +1.2VDD, and +1.1VDD system supplies
- VCCPD2
- VCCIO4, VCCPD4, and VREF4
- VCCPD5
MC2 contains the JTAG pins, some I/O power supply pins, and 46 FPGA I/O connections.
- VCCIO2, VREF2
- VCCIO5, VREF5
- JTAG TCK, TMS, TDI, TDO
| FPGA BANK | PINS ON MC1 | PINS ON MC2 | TOTAL | POWER SUPPLIES |
|---|---|---|---|---|
| Bank 2A | 0 | 16 | 16 | VCCIO2 (MC2-42) VCCPD2 (MC1-13) VREF2 (MC2-4) |
| Bank 4A | 47 | 0 | 47 | VCCIO4 (MC1-16) VCCPD4 (Fixed at +2.5 V) VREF4 (MC1-18) |
| Bank 5A | 0 | 15 | 15 | VCCIO5 (MC2-41) VCCPD5 (MC1-17) VREF5 (MC1-3) |
| Bank 5B | 1 | 15 | 16 | |
| Total | 48 | 46 | 94 |
Clock Pins
The Altera Cyclone V E design establishes several pins that offer dedicated access to the on-chip clock PLL inputs and outputs. These pins are shared with I/O and other functionality, but may have some limitations or restrictions. Please review Altera’s Cyclone V documentation to understand how these limitations may affect your design.
| BANK / GROUP (I/O VOLTAGE) | ZEM5305-A2 |
|---|---|
| CLKINp, CLKINn | MC2-75, MC2-77 |
| CLKOUT0 | MC1-65 |
| CLKOUT1 | MC1-67 |
Considerations for Differential Signals
The ZEM5305 PCB layout and routing has been designed with several applications in mind but, due primarily to space limitations, pair routing has not been performed. The board should still operate over a broad range of frequencies for differential standards, but may require some length matching on the peripheral for best performance. Routed lengths on the ZEM5305 PCB for routes to the expansion connector are listed in the Pins reference.
Characteristic Impedance
The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.
I/O Voltage Pins (VCCIO, VCCPD, and Vref)
Please see the section Powering the ZEM5305 for details on providing the necessary power for the I/O banks.