The XEM7010 was designed to be as compatible as possible with our XEM6010 in order to facilitate customer design migration with minimal changes. The physical dimensions and expansion connector locations are identical. The differences between these two products are highlighted below.
Note that this migration guide does not discuss differences between the Spartan-6 and Artix-7 FPGA architectures, features, capabilities, or limitations. Please consult the Xilinx documentation for more information.
128 MiB DDR2 SDRAM → 512 MiB DDR3 SDRAM
The XEM7010 has larger, faster, and more modern memory. The Xilinx memory controller on Artix-7 consumes fabric resources unlike the hard memory controller on the Spartan-6.
Clock PLL → Clock Oscillator
The XEM6010 has a Cypress CY22393 multi-output PLL that provided clock signals to the FPGA and expansion connectors. The XEM7010 has a fixed-output 200 MHz clock oscillator that provides this clock signal to the FPGA. The FPGA has on-board clock management resources which may be used to produce a wide range of clock frequencies. The expansion connector signals that were routed to the CY22393 on the XEM6010 are routed to the FPGA on the XEM7010.
Expansion Connector Differences
- The XEM6010 routed the USB I2C connections to the expansion connector enabling the use of the I2C API functions. On the XEM7010, these have been removed. In their place, the XADC pins from the FPGA have been routed. This provides expansion access to the FPGA’s internal analog-to-digital converter.
- The Rfuse signal on the XEM6010 expansion connector JP2-12 has been removed. An FPGA I/O pin has been routed to this pin on the XEM7010.
- FPGA differential pair connections have been preserved. In other words, a pair that existed on two expansion connectors on the XEM6010 are also connected to an I/O pair on the XEM7010. Route lengths, however, have changed. Please review the Pins table if this is a concern.
- I/O Voltage adjustments are no longer possible for all expansion connector pins. Pins on bank 13 of the XEM7310 are fixed at 3.3V. More information can be found on the Expansion Connectors page.
- The VCCIO requirements for various I/O standards (including LVDS) have changed from the Spartan 6 to the Artix 7, please refer to the Xilinx documentation for more details.
|JP3-4 and 6 are +1.2VDD||MC1-4 and 6 are +1.0VDD|
|JP3-8 is PLL CLK5||MC1-8 is FPGA fabric I/O|
|JP3-10 is USB_SCL||MC1-10 is XADC_VN|
|JP3-12 is USB_SDA||MC1-12 is XADC_VP|
|JP2-10 is FPGA VREF||MC2-10 is FPGA fabric I/O|
|JP2-11 is PLL CLK4||MC2-11 is FPGA fabric I/O|
|JP2-12 is FPGA Rfuse||MC2-12 is FPGA fabric I/O|