Design Checklist

Design ItemCarrier / PodSpecification Reference
I/O pins are populated accordingly (lower ordinal before higher ordinal).Both2. Pinouts and Signal Descriptions
On a standard port, signals capable of differential I/O must be connected before signals which are single-ended only.Both2. Pinouts and Signal Descriptions
On a standard port, differential I/O are limited to pins 5-20.Both2. Pinouts and Signal Descriptions
On a standard port, differential I/O must be populated with the positive (P) pin of the pair on the lower ordinal I/O.Both2. Pinouts and Signal Descriptions
The pod and carrier include the required mounting holes.Both3. Mechanical
3.2. Standard Port Dimensions (Carrier)
3.4. Transceiver Port Dimensions (Carrier)
Pods and carriers use the specified Samtec connectors.Both3.1. Connectors
Pods and carriers use the recommended connector placement.Both3.2. Standard Port Dimensions (Carrier)
3.4. Transceiver Port Dimensions (Carrier)
The carrier includes a SmartVIO controller.Carrier1.4.2. Carrier
The SmartVIO controller is connected via I2C to all ports on a carrier.Carrier1.4.2. Carrier
The carrier includes a host (typically an FPGA).Carrier1.4.2. Carrier
The carrier includes +3.3V, +5V, and adjustable VIO rails for peripheral power.Carrier4.2. Power Supplies
The +3.3, +5V, and VIO rails on the carrier follow the required startup sequencing.Carrier4.3 Supply Sequencing
The carrier includes one or more VIO group which share the same VIO power rail. Carrier4.2.1. VIO Supply
All transciever lanes on TXR2 and TXR4 ports are connected to transceiver-capable pins on the host.Carrier2.4. Transceiver Pod/Port Pinout (TXR-4)
AC-coupling capacitors are *not* included on transceiver lanes on the carrier.Carrier2.5. Transceiver Pod/Port Signal Description
Each port includes a unique R_GA geographical address resistor.Carrier5. SYZYGY DNA
Pod dimensions include the required width.Pod3. Mechanical
The pod includes an MCU with non-volatile storage to describe the pod’s functionality.Pod1.4.3. Pod
The pod does not output any signals to the carrier until the VIO supply has been enabled by the carrier.Pod2.2. Standard Pod/Port Signal Description