Design Checklist

Carrier Design Checklist

Design ItemRequirementSYZYGY Specification Reference
I/O pins are populated accordingly (lower ordinal before higher ordinal).Yes
P2C and C2P differential clock pairs are connected to appropriate clock I/O pins on the FPGA.Yes

Peripheral Design Checklist

Design ItemRequirementSYZYGY Specification Reference
I/O pins are populated accordingly (lower ordinal before higher ordinal).Yes
P2C and C2P differential clock pairs are connected to appropriate clock I/O pins on the FPGA.Yes