The SYZYGY specification is intended to provide broad hardware compatibility between carriers and peripherals. However, with the increasing complexity of FPGA devices and interface standards, universal compatibility cannot be guaranteed for every combination of peripheral and carrier port. The following considerations should be made when determining compatibility for your application.

The SYZYGY specification includes one standard type pinout (STD) and two transceiver type pinouts (TXR2 and TXR4). The TXR4 pinout includes two additional transceiver channels which take the place of standard I/O pins on the TXR2 pinout.

A TXR2 peripheral may be connected to a TXR4 carrier port if the following condition is met:

• No I/O signals are present on pins 25-32 (S10-S17) of the TXR2 peripheral.

A TXR4 peripheral may be connected to a TXR2 carrier port if the following condition is met:

• No transceiver signals are present on pins 25-32 (RX2P/N, TX2P/N, RX3P/N, TX3P/N) of the TXR4 peripheral.

Designers and manufacturers are encouraged to use the TXR4 pinout in all new carrier designs. The TXR2 pinout is considered legacy and is being phased out in favor of the TXR4 pinout for broadest peripheral support.

Note that standard peripherals may be socketed into transceiver ports (and vice versa) due to the mechanical similarities between the connectors. However, the power and signal pins will not align properly, and this may cause physical damage to the connectors or electrical damage to the carrier and peripheral and therefore should be avoided.

The SYZYGY specification does not require a carrier to fully populate all I/O pins on a port. However, ports and peripherals are both required to populate I/O in order of pin number with lower-ordinal pins populated first. Pin skipping is not allowed. I/O count is included in the compatibility table published by the manufacturer and therefore exactly defines which I/O pins are available (for a carrier) or required (for a peripheral).

The SmartVIO function determines a compatible VIO voltage for all peripherals connected to the same VIO group on a carrier. If a compatible voltage is not found, the carrier does not enable VIO for that group.

Carrier and peripheral manufacturers are encouraged to design a usable VIO range as wide as possible. On carriers, this ideally includes 1.2-3.3V, although this is not always feasible given the limited voltage ranges of high-performance I/O banks on modern FPGA devices.

Peripheral manufacturers are encouraged to include voltage level translation on designs which would otherwise have limited VIO range, when possible. See “VIO Voltage Translation”. This approach provides the broadest range of compatibility with other peripherals that an integrator may wish to use on other ports within the same group.

I/O voltage standards commonly range from 1.2-3.3V, but not all FPGA devices support this I/O voltage range. For example, HP banks on Xilinx 7-series and UltraScale devices support a maximum I/O voltage of 1.8V.

For the broadest carrier compatibility, SYZYGY peripheral designers are encouraged to include voltage level translation where feasible. This allows the peripheral to interface to a broad range of carrier ports and is especially useful when the peripheral would otherwise support only a narrow I/O voltage range or even a single I/O voltage. For example, SFP and QSFP interfaces are specified to use 3.3V I/O for some of the interface and control signals.

Peripheral designers should consider potential VIO restrictions when interfaces include LVDS signals. For example, some Xilinx FPGA families use two different LVDS standards depending on the bank type: 1.8V LVDS for high-performance banks and 2.5V LVDS for high-range banks. Designing the peripheral to operate across a wide range of VIO voltages is encouraged. This may necessitate the use of level translation, and it may also require rebiasing of LVDS signals in order to meet the common-mode requirements of the carrier FPGA.

The SYZYGY specification does not include requirements for length or skew (i.e. propagation delay) matching of signals on either the carrier or peripheral. For many applications this is not a problem because matching is not often required for the types of interfaces targeted by the SYZYGY specification.

In order to provide the broadest range of compatible peripheral applications, carrier manufacturers are encouraged to match the I/O signals (both single-ended and differential) on standard and transceiver ports to within a reasonable length/skew range – for example, 100 mils or approximately 15-18 ps (including any package skew within the FPGA). This would only apply to the signals within a single port – matching skew between ports is generally not required. It is recommended to match the P/N signals in a differential I/O pair to within 10 mils, or approximately 1.5-1.8 ps (including package skew).

Carrier manufacturers should consider publishing per-trace PCB lengths (or skews) for all I/O and transceiver routing, as well as the internal package delays of the FPGA. This should be published separately from the compatibility table (which is meant to provide only a summary) but should be accessible by customers who need to determine compatibility with peripherals that have skew requirements.

In some cases, SYZYGY compatibility does not imply universal compatibility between a particular SYZYGY-compliant peripheral and all SYZYGY-compliant carriers, even if the corresponding compatibility tables provide a match.

Some peripheral interfaces may require special functions which are available only on certain FPGA pins. For example, MIPI requires use of DBC (Dedicated Byte Clock) or QBC (Quad Byte Clock) pins on supporting Xilinx FPGAs. SYZYGY carrier boards built with these FPGAs may not provide DBC or QBC pins to all SYZYGY ports.

Not all TXR4 ports may have the same capabilities since some hard IP blocks may only be accessible via certain transceiver quads. For example, a hard PCIe block may only be accessible from some of the quads in an FPGA, and those quads will need to be connected to the TXR4 port in order for that port to operate with a SYZYGY PCIE peripheral.

Similarly, some peripheral interfaces to Xilinx carrier boards may require access to the VRP voltage reference pin, which may or may not be available to the peripheral.

Ultimately, it is up to the end-user to determine carrier-peripheral compatibility for these specialized use cases. We recommend that carrier and peripheral manufacturers make any specialized compatibility abundantly clear to customers to avoid any confusion.

There is broad general support for LVDS capability on FPGA devices, but certain restrictions may be encountered. For example:

• HD banks on Xilinx UltraScale device families do not support LVDS output. LVDS input on these banks requires external termination.
• Some older Intel device families (Cyclone V, for example) do not include bidirectional LVDS pins. Instead, LVDS pins are defined as receive-only or transmit-only.
• Some newer Intel device families (Cyclone 10, for example) include pins which support emulated LVDS with an additional requirement of external termination.

Double-wide peripherals allow twice as many I/O signal connections as a single peripheral of the same type. If a double-wide peripheral design does not require all available I/O, it is recommended to split the utilized I/O evenly between the two connectors. This will provide the broadest compatibility with carrier ports that do not have fully populated I/O.

SYZYGY is intended as an FPGA interface specification. Due to limitations that are typical of FPGA SoC I/O pins, it is not recommended to use an SoC for SYZYGY port interfaces on carriers.

If SoC I/O pins are used in a carrier design, the following limitations may need to be considered:

• Lack of LVDS differential pair I/O
• Fixed pinout locations for certain interface types (i.e. USB, Gigabit Ethernet, SD card interface, etc.)
• Limited internal routing options