Start a State Machine
Starting state machines is best done with Trigger Ins. To use a trigger to initiate an event, check for the trigger in a block synchronized with the clock on which the trigger is operating. The triggers in okTriggerxx are active high. You do not need to instantiate a new okTriggerxx for each trigger bit, since each bit can be triggered separately using its unique FrontPanel endpoint address. In the following example, reset and start are dependent on two separate trigger endpoints, but you can also use a single trigger endpoint and pass different values to it using ActivateTriggerIn. You can then base the values of start and reset on the value sent to the trigger endpoint.
When initializing a state machine, it is recommended but not required that you define a reset signal. In this example, the reset is attached to a trigger, but it can also be attached to a wire.
The pauses in the example are included to make the LEDs readable and are not required for the triggers to operate properly.
Note: This section contains both software and HDL portions. The software and HDL must work in tandem if FrontPanel is to be used on the PC end to perform tasks on the FPGA. The HDL in this section is designed to be set within the FrontPanel Framework HDL, available on the HDL Framework page for USB 2.0 and USB 3.0. For specific information about each of these methods or modules, consult the FrontPanel User’s Manual, the FrontPanel API guide, and the samples and README files provided with the FrontPanel download.
C/C++
okCFrontPanel dev;
okCFrontPanel.ErrorCode error;
dev.OpenBySerial();
error = dev.ConfigureFPGA("example.bit");
while (1){
// Trigger state machine
dev.ActivateTriggerIn(0x40, 0);
std::this_thread::sleep_for(std::chrono::seconds(1));
std::cout << "Hitn";
}Code language: PHP (php)C#
okCFrontPanel dev = new okCFrontPanel();
okCFrontPanel.ErrorCode error = new okCFrontPanel.ErrorCode();
dev.OpenBySerial("");
error = dev.ConfigureFPGA("example.bit");
while (true)
{
// Trigger state machine
dev.ActivateTriggerIn(0x40, 0);
Thread.Sleep(1000);
Console.WriteLine("Hit.");
}Code language: JavaScript (javascript)Python
dev = ok.okCFrontPanel()
dev.OpenBySerial(“”)
error = dev.ConfigureFPGA("example.bit")
while 1 == 1:
# Trigger state machine
dev.ActivateTriggerIn(0x40, 0)
time.sleep(1)
print "Hit."Code language: PHP (php)Java
public class example{
okCFrontPanel dev;
okCFrontPanel.ErrorCode error;
Thread t;
public void Initialize(){
t = new Thread();
dev = new okCFrontPanel()
dev.OpenBySerial(“”);
error = dev.ConfigureFPGA(“example.bit”);
// It’s a good idea to check for errors here!
}
public void Hit(){
// Trigger state machine
dev.ActivateTriggerIn(0x40, 0);
try{ Thread.sleep(1000); }
catch(Exception e){ System.out.println(e); }
System.out.println(“Hit.”);
}
}Code language: PHP (php)Verilog
// Wire declarations
wire [15:0] start;
wire [15:0] treset;
// Circuit behavior
integer state;
parameter
s_idle = 1,
s_state1 = 2,
s_state2 = 3;
always @(posedge clk1) begin
case (state)
s_idle: begin
if (start[0]) begin
state <= s_state1;
led <= 8’hAA;
end
end
s_state1: begin
if (start[0]) begin
state <= s_state2;
led <= 8’h55;
end else if (treset) begin
state <= s_idle;
led <= 8’h00;
end else begin
state <= s_state1;
led <= 8’hAA;
end
end
s_state2: begin
if (start[0]) begin
state <= s_state1;
led <= 8’hAA;
end else if (treset) begin
state <= s_idle;
led <= 8’h00;
end else begin
state <= s_state2;
led <= 8’h55;
end
end
default: begin
state <= s_idle;
led <= 8’h00;
end
endcase
end
// FrontPanel endpoint instantiation
okTriggerIn smstart(
.ok1(ok1),
.ep_addr(8'h40),
.ep_clk(clk1),
.ep_trigger(start)
);
okTriggerIn smreset(
.ok1(ok1),
.ep_addr(8'h42),
.ep_clk(clk1),
.ep_trigger(treset)
);Code language: PHP (php)VHDL
--Wire declarations
signal count : STD_LOGIC_VECTOR(7 downto 0);
signal start_vector : STD_LOGIC_VECTOR(15 downto 0);
signal state_is : STD_LOGIC_VECTOR(15 downto 0);
signal start : STD_LOGIC;
signal t_reset : STD_LOGIC;
--States
signal state : STD_LOGIC_VECTOR(7 downto 0) := x"01";
constant s_idle : STD_LOGIC_VECTOR(7 downto 0) := x"01";
constant s_state1 : STD_LOGIC_VECTOR(7 downto 0) := x"02";
constant s_state2 : STD_LOGIC_VECTOR(7 downto 0) := x"03";
-- Circuit behavior
start <= start_vector(0);
t_reset <= start_vector(1);
process(clk1, t_reset) begin
if (t_reset = '1') then
state <= s_idle;
led <= x"00";
end if;
if rising_edge(clk1) then
case(state) is
when s_idle =>
if(start(0) = '1') then
state <= s_state1;
led <= x"AA";
else
state <= s_idle;
led <= x"00";
end if;
when s_state1 =>
if(start(0) = '1') then
state <= s_state2;
led <= x"55";
elsif(t_reset = '1') then
state <= s_idle;
led <= x"00";
else
state <= s_state1;
led <= x"AA";
end if;
when s_state2 =>
if(start(0) = '1') then
state <= s_state1;
led <= x"AA";
elsif(t_reset = '1') then
state <= s_idle;
led <= x"00";
else
state <= s_state2;
led <= x"55";
end if;
when others =>
state <= state;
end case;
end if;
end process;
-- FrontPanel endpoint instantiation
tcount : okTriggerIn port map(
ok1=>ok1,
ep_addr=>x"40",
ep_clk=>clk1,
ep_trigger=>start_vector
);Code language: PHP (php)