Setting and Getting Registers

Setting and Getting registers are both done on the PC. To set a register, use the okCFrontPanel method WriteRegister(). To get a register from the FPGA, use the okCFrontPanel method ReadRegister(). Both of these methods use the okTRegisterEntry class, which defines the structure of a register entry.

When defining the register storage space in HDL, you can separate it into blocks so that different addresses go to different register blocks. For example, you can define a register block that behaves as a stack and a separate space containing general purpose registers without generating conflicts. In this example, only data that has 0x00 in the most significant byte will be stored and other register data is ignored. OkRegisterBridge is unique among the FrontPanel endpoints in that it does not have an endpoint address. Instead, registers are read and written by referencing a data address, which is the same for both read and write operations.

Note: In Python, ReadRegister takes in an address value and returns the value from the address in memory. It does not take the destination as an argument.

This module can be tested with the “Accessing BRAM” example code or the included HDL. For specific information about of the FrontPanel methods and modules, consult the FrontPanel User’s Manual, the FrontPanel API guide, and the samples and README files provided with the FrontPanel download.

Note: This section contains both software and HDL portions. The software and HDL must work in tandem if FrontPanel is to be used on the PC end to perform tasks on the FPGA. The HDL in this section is designed to be set within the FrontPanel Framework HDL, available on the HDL Framework page for USB 2.0 and USB 3.0. For specific information about the FrontPanel methods or modules, consult the FrontPanel User’s Manual, the FrontPanel API guide, and the samples and README files provided with the FrontPanel download.

C/C++

okCFrontPanel dev; okTRegisterEntry reg; reg.address = 0x01; reg.data = 0x0000; dev.OpenBySerial(); dev.ConfigureFPGA("example.rbf"); dev.WriteRegister(reg.address, 0x000A); dev.ReadRegister(reg.address, ®.data);
Code language: JavaScript (javascript)

C#

okCFrontPanelDevices devices = new okCFrontPanelDevices(); okCFrontPanel dev = devices.Open(""); dev.ConfigureFPGA("example.rbf"); dev.WriteRegister(0x01, 0x000A); uint data; dev.ReadRegister(0x01, out data);
Code language: JavaScript (javascript)

Python

dev = ok.okCFrontPanel() reg = ok.okTRegisterEntry() reg.address = 0x0001 dev.OpenBySerial("") dev.ConfigureFPGA("example.rbf") dev.WriteRegister(reg.address, 0x000A) reg.data = dev.ReadRegister(reg.address)
Code language: JavaScript (javascript)

Java

public class example{ okCFrontPanel dev; okCFrontPanel.ErrorCode error; long[] data = {0}; int i; public void ReadWrite(){ dev = new okCFrontPanel(); dev.OpenBySerial(""); error = dev.ConfigureFPGA("example.rbf"); //It’s a good idea to check for errors here!! dev.WriteRegister(0x01, 0x01); dev.ReadRegister(0x01, data); } }
Code language: PHP (php)

Verilog

// Wire declarations wire [31:0] regAddress; wire [31:0] regDataOut; reg [31:0] regStore[31:0]; reg [31:0] regDataIn; wire regRead; wire regWrite; wire [7:0]regBlock; wire [7:0]regWord; // Circuit behavior assign regBlock = regAddress[31:24]; assign regWord = regAddress[7:0]; //Define a block with a limited register range to store data always @ (posedge okClk) begin if(regWrite) begin if(regBlock == 8'h00) begin regStore[regWord] <= regDataOut; end end else if (regRead) begin if(regBlock == 8'h00) begin regDataIn <= regStore[regWord]; end end end // FrontPanel endpoint instantiation okRegisterBridge regBridge ( .okHE(okHE), .okEH(okEHx[0*65 +: 65]), .ep_write(regWrite), .ep_read(regRead), .ep_address(regAddress), .ep_dataout(regDataOut), .ep_datain(regDataIn) );
Code language: PHP (php)

VHDL

--Signal declarations signal regAddress : STD_LOGIC_VECTOR(31 downto 0) := x"00000000"; signal regDataOut : STD_LOGIC_VECTOR(31 downto 0); signal regDataIn : STD_LOGIC_VECTOR(31 downto 0) := x"00000000"; signal regRead : STD_LOGIC; signal regWrite : STD_LOGIC; signal writeEn : STD_LOGIC_VECTOR(3 downto 0); --Component declaration goes in architecture portion of VHDL body COMPONENT BRAM_Macro PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; --Circuit behavior process (regWrite) begin if(regWrite = '1') then writeEn <= "1111"; else writeEn <= "0000"; end if; end process; --Instantiate Block RAM Xilinx Core IP BRAM_inst : BRAM_Macro port map( wea => writeEn, addra => regAddress, dina => regDataOut, douta => regDataIn, clka => okClk ); --FrontPanel endpoint instantiation regBridge : okRegisterBridge port map( okHE=>okHE, okEH=>okEHx(1*65-1 downto 0*65), ep_write=>regWrite, ep_read=>regRead, ep_address=>regAddress, ep_dataout=>regDataOut, ep_datain=>regDataIn );
Code language: PHP (php)