Logic Registers (USB 2.0)

The SetWireInValue and GetWireOutValue methods in the okCFrontPanel class allow you to set and get up to 16-bit bus values across the entire defined Wire address space (0x00-0x1F for WireIn, 0x20-0x3F for WireOut). You can set the WireIn values by passing in the address of the WireIn and its new value. You can read WireOut values by passing the address of the WireOut and a bit mask to extract only the relevant bits. After setting a wire in value and before reading a wire out value, remember to update the WireIns and WireOuts, respectively. Otherwise, the values will not be accurate.

These techniques are also available on USB 3.0 devices, but those devices include the okRegisterBridge module along with methods and structs for reading registers. If you are using Wires on a USB 3.0 device, note that instead of 16-bit bus values, you can set and get up to 32-bit bus values.

Note: This section contains both software and HDL portions. The software and HDL must work in tandem if FrontPanel is to be used on the PC end to perform tasks on the FPGA. The HDL in this section is designed to be set within the FrontPanel Framework HDL, available on the HDL Framework page for USB 2.0 and USB 3.0. It is assumed that the FPGA is configured with the bitfile generated by the HDL before the hardware is run. For specific information about each of these methods or modules, consult the FrontPanel User’s Manual, the FrontPanel API guide, and the samples and README files provided with the FrontPanel download.

C/C++

okCFrontPanel dev; UINT32 A; // Send 0x0A to wire at endpoint 0x03 dev.OpenBySerial(); dev.SetWireInValue(0x03, 0x0A); dev.UpdateWireIns(); // Read value from WireOut endpoint at 0x20 dev.UpdateWireOuts(); A = dev.GetWireOutValue(0x20);
Code language: JavaScript (javascript)

C#

okCFrontPanel dev = new okCFrontPanel(); UInt32 A; // Send 0x0A to wire at endpoint 0x03 dev.OpenBySerial(""); dev.SetWireInValue(0x03, 0x0A); dev.UpdateWireIns(); // Read value from WireOut endpoint at 0x20 dev.UpdateWireOuts(); A = dev.GetWireOutValue(0x20);
Code language: JavaScript (javascript)

Python

dev = ok.okCFrontPanel() # Send 0x0A to wire at endpoint 0x03 dev.OpenBySerial("") dev.SetWireInValue(0x03, 0x0A) dev.UpdateWireIns(); # Read value from WireOut endpoint at 0x20 dev.UpdateWireOuts() A = dev.GetWireOutValue(0x20)
Code language: PHP (php)

Java

public class example{ okCFrontPanel dev; long A; okCFrontPanel.ErrorCode error; public void Initialize(){ dev = new okCFrontPanel(); dev.OpenBySerial(""); error = dev.ConfigureFPGA("example.bit"); // It’s a good idea to check for errors here! } public void SetWires(){ // Send 0x0A to wire at endpoint 0x03 dev.SetWireInValue(0x03, 0x0A); dev.UpdateWireIns(); } public long GetWires(){ // Read value from WireOut endpoint at 0x20 dev.UpdateWireIns(); A = dev.GetWireOutValue(0x20); return A; } }
Code language: PHP (php)

Verilog

// Circuit behavior assign led <= count_by[7:0]; always @ (posedge ti_clk) begin counter <= counter + count_by; end // FrontPanel module instantiation okWireIn inA( .ok1(ok1), .ep_addr(8'h03), .ep_dataout(count_by) ); okWireOut outA( .ok1(ok1), .ok2(ok2x[0*17 +: 17]), .ep_addr(8'h20), .ep_datain(counter) );
Code language: PHP (php)

VHDL

-- Circuit behavior led <= not dataA (7 downto 0); process (ti_clk) begin counter <= counter + count_by; end process; -- FrontPanel module instantiation inA : okWireIn port map( ok1=>ok1, ep_addr=>x"03", ep_dataout=>dataA ); outA : okWireOut port map( ok1=>ok1, ok2=>ok2s( 1*17-1 downto 0*17 ), ep_addr=>x"20", ep_datain=>dataA );
Code language: PHP (php)