HDL Framework (USB 2.0)

This section contains template definitions of the top-level module for FrontPanel-enabled USB 2.0 devices in Verilog and VHDL. It is applicable to the examples for Wires, Triggers, and Pipes. This boilerplate is familiar if you’ve looked through our samples. To keep the examples brief, we won’t duplicate this code for each one.

Verilog

module Framework(
     input wire[7:0] hi_in,
     output wire [1:0] hi_out,
     inout wire [15:0] hi_inout,
     inout wire hi_aa,
     output wire hi_muxsel,
     output reg [7:0] led,
     input wire clk1
 
     // Your I/O here
     );
 
     wire ti_clk;
     wire [15:0] dataA;
     wire [31:0] counter;
     wire [15:0] count_by;
     wire [16:0] ok2;
     wire [30:0] ok1;
     wire [4*17-1:0] ok2x;
     // Adjust size of ok2x to fit the number of outgoing FrontPanel endpoints in your design [n*17-1:0]
 
     // Your wires here
	 
     assign hi_muxsel = 1'b0;
 
     //Your circuit behavior here
 
     // Adjust N to fit the number of outgoing FrontPanel endpoints in your design (.N(n))
     okWireOR # (.N(4)) wireOR (ok2, ok2x);
	 
     //Host interfaces directly with FPGA pins
     okHost okHI( 
          .hi_in(hi_in),
          .hi_out(hi_out),
          .hi_inout(hi_inout),
          .hi_aa(hi_aa),
          .ti_clk(ti_clk),
          .ok1(ok1),
          .ok2(ok2)
     );
 
     // Your FrontPanel module instantiations here
endmoduleCode language: Verilog (verilog)

VHDL

use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_unsigned.all;
use work.FRONTPANEL.all;
 
entity Framework is
     port (
          hi_in : in STD_LOGIC_VECTOR(7 downto 0);
          hi_out : out STD_LOGIC_VECTOR(1 downto 0);
          hi_inout : inout STD_LOGIC_VECTOR(15 downto 0);
          hi_aa : inout STD_LOGIC;
		
          hi_muxsel : out STD_LOGIC;
          led : out STD_LOGIC_VECTOR(7 downto 0);
          clk1 : in STD_LOGIC
 
          -- Your I/O here
	);
end Framework;
 
architecture Behavioral of Framework is
     signal ti_clk : STD_LOGIC;
     signal ok : STD_LOGIC_VECTOR(30 downto 0);
     signal ok2 : STD_LOGIC_VECTOR(16 downto 0);
     signal ok2s : STD_LOGIC_VECTOR(17*4-1 downto 0);
     -- Adjust size of ok2s to fit the number of outgoing FrontPanel endpoints in your design (17*n-1 downto 0) 
	
     --Circuit signals here--
 
begin
hi_muxsel  <= '0';
 
--Circuit behavior and instantiations here--
 
okHI : okHost port map (
          hi_in=>hi_in,
          hi_out=>hi_out,
          hi_inout=>hi_inout,
          hi_aa=>hi_aa,
          ti_clk=>ti_clk,
          ok1=>ok1,
          ok2=>ok2
);
 
-- Adjust N to fit the number of outgoing FrontPanel endpoints in your design (N=>n)	
okWO : okWireOR generic map (N=>1) port map (ok2=>ok2, ok2s=>ok2s);
 
-- Your FrontPanel module instantiations here
 
end Behavioral;Code language: VHDL (vhdl)