The 1-GiByte DDR4 SDRAM provides a 16-bit wide data interface and is connected to the 1.2-V I/O on HP bank 66 of the FPGA. The maximum data rate of the SDRAM is 2666 Mb/s, although the speed grade of the Artix UltraScale+ will limit the maximum supported data rate to what is stated in Table 27 of DS931. The -2 speed grade on the XEM8305-AU25P supports a maximum data rate of 2400 Mb/s. This gives a supported peak memory bandwidth of 38.4 Gb/s.

The following resources are available to help provide guidance for designs that involve this memory:

• How-To Apply DDR MIG Settings and Vivado Board File to generate AMD’s MIG IP Core.
• The RAMTester sample reads and writes this memory via FrontPanel pipe endpoints.
• The XEM8305 Pins Reference can generate a constraints file (click on Export) with complete pin mapping and I/O constraints for use in your design.

Artix UltraScale+ devices support external, high-performance memory through the use of the Memory Interface Generator (MIG) provided by AMD. MIG produces a custom memory interface core that may be included in your design. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

All settings are based on the DDR4 SDRAM (MIG) v2.2 IP and Vivado 2023.1.

The FPGA to DDR4 pin mappings are shown below. These are also available in the Pins Reference when exporting a constraints file as well as the sample designs that utilize the memory.