BRK8305 Breakout Board

Unlike our integration modules, breakout boards are not intended for production integration. We reserve the right to change dimensions and functionality of this board at any time and may not necessarily have the previous version available for purchase.

Peripherals and Connectors

The table below summarizes the various connectors on the BRK8305. The XEM8305 Pin List has connection information in the BRK8305 column. Additionally, please refer to the schematics and layout available on the Downloads section of the Pins website for detailed connection diagrams.

PCIEJ6GTY224, GTY225TxRx 0-3
QSFPJ30GTY226TxRx 0-3
2mm HeaderMC4Bank 64, 84
2mm HeaderMC5Bank 64
2mm HeaderMC6Bank 85, 86
JTAG HeaderJ3JTAG Pins

Power Connectors

The BRK8305 has two power connectors. Only one power connection should be used at a time. Powering the device with multiple sources may cause damage.

The BRK8305 has a barrel jack power connector (J4) and a 6-pin PCIe connector (J5) that accept 5V to 15V, 12V nominal. This input voltage is passed to the XEM8305’s expansion connector.

Barrel Jack Power Connector

The barrel jack power connector on the BRK8305 is part number PJ-102AH from CUI, Inc. It is a standard “canon-style” 2.1mm / 5.5mm jack. The outer ring is connected to DGND, the center pin is +VDCIN. The PJ-102AH jack is rated for 5 A maximum continuous current.

6-Pin Power Connector

The 6-pin connector is a PCIe-style power connector from Molex, part number 0455580003. Pins 1-3 are connected to +VDCIN, and pins 4-6 are connected to DGND. Maximum current is 24 A (8 A per pin).


The BRK8305 has a built in USB JTAG adapter. Connect to the USB-C connector J500 for AMD tools compatible access to the XEM8305’s JTAG interface.

The JTAG connections are also wired to a dedicated 2mm header J501 that can be used with a compatible JTAG cable. The JTAG interface presented is at a 1.8V signaling voltage. This header is not populated by default. This footprint is compatible with the Molex part 87831-1420.

1GND2+1.8V (Vref)

PCIE Connector Fin

The BRK8305 is designed to slot into a standard computer PCIE x8 and larger connector. This allows for a high bandwidth PCIE host connection.

PCIE Lanes

The BRK8305 supports up to a x8 PCIE connection and is configured for x8 lanes by default. This is the maximum PCIE width supported by Artix UltraScale+. For more information see the PG213 section ‘Artix UltraScale+ Devices Available GT Quads’.

A x1 or x4 lane connection can be configured if required. To change the configured number of lanes, place the PCIE_PRSNT jumper resistor in the appropriate location as defined in the table on the BRK8305 schematic.

Control Signals

Voltage level shifting of PERST, WAKE and SMBus signals to the host is handled on the BRK8305 to change the signals from the I/O voltage level to 3.3V used by the PCIE fin. Control IO signals across the connector are disabled if either side is unpowered.

SignalExpansion Connector PinFPGA PinVCCO
WAKEMC2 – 17J10VCCO_85
SDA (SMBus)MC2 – 13K9VCCO_85
SCL (SMBus)MC2 – 11K10VCCO_85

ADC Voltage Reference

By default BRK8305 includes a 0R jumper that enables the XEM8305 FPGA’s internal ADC voltage reference. However part footprints are included for adding an external high precision reference voltage IC if required.

To use the external 1.25V voltage reference part REF3012AIDBZT or compatible:

  • Remove jumper resistor R6
  • Place voltage reference U1
  • Place capacitors C1, C2 and C3
  • Place jumper resistor R5


A QSFP+ port is connected to the XEM8305’s quad 226 transceiver to allow for easy connection of QSFP+ modules. Full QSFP+ transceiver connection pinout and control signal I/O connections are listed on the XEM8305 Pin List.


To facilitated common QSFP+ protocols a 156.25Mhz oscillator is included on the BRK8305 and connected to the XEM8305’s quad 226 refclk 0 input.


Control Signals

Voltage level shifting of the QSFP+ signals to the host is handled on the BRK8305 to change the signals from the I/O voltage level to 3.3V used by the QSFP+ module. Control IO signals across the connector are disabled if either side is unpowered.

INT_BMC2 – 19J9VCCO_85
SDAMC2 – 29G9VCCO_85
SCLMC2 – 31F10VCCO_85

Clock Oscillators

The XEM8305 provides three MGT refclock inputs on its expansion connectors. This table lists the refclock connections on the BRK8305.

REFCLOCKFPGA PINFreqencyDesignator
REFCLK0P 224 / REFCLK0N 224AB7 / AB6User Input SE ClockJ1
REFCLK0P 225 / REFCLK0N 225V7 / V6PCIE Host RefclockJ6
REFCLK0P 226 / REFCLK0N 226P7 / P6156.25MhzU3

The Quad 224 refclock0 input uses a single ended to LVDS converter onboard the BRK8305. A 3.3V single ended clock of the desired frequency can be connected to the U.FL connector J1, and it will be converted to an LVDS refclock input.

PCIE Bracket

The BRK8305 is designed to slot into a standard x8 or larger PCIE slot. It has mounting holes to attach a PCIE bracket for mechanical support. The PCIE bracket requires a cutout for the QSFP port. A mechanical drawing is provided below. Attaching the bracket to the BRK8305 requires two 5/32″ long 4-40 machine screws.

The PCIE bracket is not provided by Opal Kelly at this time.

Mechanical Drawing

Impedance and Length Matching

Single-ended fabric I/O are routed to the breakout connectors with 50Ω characteristic impedance. Differential fabric I/O and transceiver signals are routed to the breakout connectors as pairs with 100Ω differential impedance.

Schematic and Design Files

The BRK8305 schematics and design files are available in the Downloads section of the Pins website.

Mechanical Drawing

The mechanical drawing below may be used for enclosure or mounting hardware design. 3D Models are also available in SolidWorks, STEP, and IGES formats.