Expansion Connectors

Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (QSF) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the ZEM5310 may be found at the link to the right. 

 

Expansion Connectors

Two high-density, 120-pin expansion connectors are available on the bottom-side of the ZEM5310 PCB.  These expansion connectors provide user access to several power rails on the ZEM5310, the JTAG interface on the FPGA, and 106 dedicated I/O pins on the FPGA, including several CLK and CLKOUT pins.

The connectors on the ZEM5310 are Samtec part number: BSE-040-01-F-D-A.  The table below lists the appropriate Samtec mating connectors along with the total mated height. The BTE-040-01-F-D-A part is used on the BRK5310 breakout board.

SAMTEC PART NUMBERMATED HEIGHT
BTE-040-01-F-D-A5.00mm (0.197″)
BTE-040-02-F-D-A8.00mm (0.315″)
BTE-040-03-F-D-A11.00mm (0.433″)
BTE-040-04-F-D-A16.10mm (0.634″)
BTE-040-05-F-D-A19.10mm (0.752″)

FPGA Connections

MC1 contains most of the system power supply pins in addition to 47 FPGA I/O connections. Please see the ZEM5310 Pins Reference for details.

  • +VDCIN from the power connector
  • +2.5VDD, +1.8VDD, and +1.2VDD system supplies
  • VCCPD_MC1
  • VCCIO_MC1
  • VREF_MC1

MC2 contains the JTAG pins, some I/O power supply pins, and 59 FPGA I/O connections. Note that MC2 pins 61, 63, and 65-74 are powered by a fixed 1.5V I/O voltage. This may not be changed.

  • +2.5VDD, +1.8VDD, and +1.2VDD system supplies
  • VCCPD_MC2
  • VCCIO_MC2
  • VREF_MC2
  • VCCIO5, VREF5
  • JTAG TCK, TMS, TDI, TDO
FPGA BANKPINS ON MC1PINS ON MC2TOTALPOWER SUPPLIES
Bank 2A16016VCCIO_MC1 / VCCPD_MC1
Bank 4A04848VCCIO_MC2 / VCCPD_MC2
Bank 5A16016VCCIO_MC1 / VCCPD_MC1
Bank 5B15116VCCIO_MC1 / VCCPD_MC1
Bank 7A066Fixed 1.5V I/O
Bank 8A044Fixed 1.5V I/O
Total4759106

Clock Input Pins

Available clock input pins are illustrated in the table below.

FPGA BANKVCCIOFPGA PINSMCX PINS
Bank 5BVCCIO_MC1N16
M16
MC1:77
MC1:79
Bank 4AVCCIO_MC2V15
V14
MC2:77
MC2:79
Bank 4AVCCIO_MC2W16
V16
MC2:41
MC2:43

Setting I/O Voltages

The Cyclone V FPGA allows users to set I/O bank voltages in order to support several different I/O signal standards. This functionality is supported on the ZEM5310 by allowing the user to connect independent supplies to the FPGA VCCIO and VCCPD pins on the expansion connectors.

By default, ferrite beads have been installed that attach each VCCIO and VCCPD net to the +2.5VDD supply. If you intend to supply power to a particular I/O bank, you MUST remove the appropriate ferrite beads. Power can then be supplied through the expansion connectors.

Note that Altera has a number of restrictions on allowable VCCIO voltage ranges and the required VCCPD voltages for specific VCCIO settings. These restrictions are described in detail in the Altera Cyclone V documentation and on the Powering the ZEM5310 page, under “I/O Triples”.

The table below lists details for user-supplied I/O bank voltages.

SUPPLY NETFPGA BANKSFERRITE BEAD
VCCPD_MC12A, 5A, 5BFB15
VCCPD_MC23A, 3B, 4AFB16
VCCIO_MC12A, 5A, 5BFB14
VCCIO_MC24AFB13

Considerations for Differential Signals

The ZEM5310 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs.  Please refer to the Altera Cyclone V documentation for details on using differential I/O standards with the FPGA.

FPGA I/O Bank Voltages

In order to use differential I/O standards with the Cyclone V, you must set the VCCPD and VCCIO voltages for the appropriate banks according to the specifications in the Altera Cyclone V documentation.  Please see the section above entitled “Setting I/O Voltages” for details.

Characteristic Impedance

The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.

Differential Pair Lengths

In many cases, it is desirable that the route lengths of a differential pair be matched within some specification.  Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.

Reference Voltage Pins (Vref)

The Altera Cyclone V supports externally-applied input voltage thresholds for some input signal standards. The ZEM5310 supports these Vref applications for banks 2A, 4A, 5A, and 5B. Please see the Altera Cyclone V documentation for more details. In summary,

FPGA BANKVREFFPGA PINSMCX PINNOTES
2A, 5A, 5BVREF_MC1W1, R20, L20MC1:10All three VREF pins of these banks are connected together to a common pin on MC1
4AVREF_MC2AB16MC2:10