Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (QSF) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the ZEM5310 may be found at the link to the right. 

Two high-density, 120-pin expansion connectors are available on the bottom-side of the ZEM5310 PCB.  These expansion connectors provide user access to several power rails on the ZEM5310, the JTAG interface on the FPGA, and 106 dedicated I/O pins on the FPGA, including several CLK and CLKOUT pins.

The connectors on the ZEM5310 are Samtec part number: BSE-040-01-F-D-A.  The table below lists the appropriate Samtec mating connectors along with the total mated height. The BTE-040-01-F-D-A part is used on the BRK5310 breakout board.

MC1 contains most of the system power supply pins in addition to 47 FPGA I/O connections. Please see the ZEM5310 Pins Reference for details.

• +VDCIN from the power connector
• +2.5VDD, +1.8VDD, and +1.2VDD system supplies
• VCCPD_MC1
• VCCIO_MC1
• VREF_MC1

MC2 contains the JTAG pins, some I/O power supply pins, and 59 FPGA I/O connections. Note that MC2 pins 61, 63, and 65-74 are powered by a fixed 1.5V I/O voltage. This may not be changed.

• +2.5VDD, +1.8VDD, and +1.2VDD system supplies
• VCCPD_MC2
• VCCIO_MC2
• VREF_MC2
• VCCIO5, VREF5
• JTAG TCK, TMS, TDI, TDO

Available clock input pins are illustrated in the table below.

The Cyclone V FPGA allows users to set I/O bank voltages in order to support several different I/O signal standards. This functionality is supported on the ZEM5310 by allowing the user to connect independent supplies to the FPGA VCCIO and VCCPD pins on the expansion connectors.

By default, ferrite beads have been installed that attach each VCCIO and VCCPD net to the +2.5VDD supply. If you intend to supply power to a particular I/O bank, you MUST remove the appropriate ferrite beads. Power can then be supplied through the expansion connectors.

Note that Altera has a number of restrictions on allowable VCCIO voltage ranges and the required VCCPD voltages for specific VCCIO settings. These restrictions are described in detail in the Altera Cyclone V documentation and on the Powering the ZEM5310 page, under “I/O Triples”.

The table below lists details for user-supplied I/O bank voltages.

The ZEM5310 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs.  Please refer to the Altera Cyclone V documentation for details on using differential I/O standards with the FPGA.

In order to use differential I/O standards with the Cyclone V, you must set the VCCPD and VCCIO voltages for the appropriate banks according to the specifications in the Altera Cyclone V documentation.  Please see the section above entitled “Setting I/O Voltages” for details.

The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.

In many cases, it is desirable that the route lengths of a differential pair be matched within some specification.  Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.

The Altera Cyclone V supports externally-applied input voltage thresholds for some input signal standards. The ZEM5310 supports these Vref applications for banks 2A, 4A, 5A, and 5B. Please see the Altera Cyclone V documentation for more details. In summary,