This reference is provided to help guide you through the design process of a mating peripheral to the XEM8305. It is not intended to be a comprehensive instruction manual. While we put forth great effort to reduce the effort required to build an FPGA-enabled platform, there are hundreds of pages of product documentation from AMD that should be considered. Use this guide as a roadmap and starting point for your design effort.

• XEM8305 Specifications
• XEM8305 Pins Reference
• Samtec ERF6 product page
• Xilinx Power Estimator

Input power to the XEM8305 must be applied through the expansion connector MC1. For more information in providing input power and the input power protections, see Powering the XEM8305. For information on expansion connector power pin assignments, see the XEM8305 Pins Reference.

The total operating power budget is an important system consideration. The power budget for the XEM8305 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

The onboard XEM8305 power supply regulators provide power for onboard systems. The Power Budget table on the Powering the XEM8305 page indicates the total current available for each supply rail. This table may be used to estimate the total amount of input power required for your design.

External power connections are required for the I/O banks VCCO rails. See the Powering the XEM8305 page for more details in the External I/O Voltage section.

Details on the available standards can be found in the following AMD documentation:

• Artix UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS931)
• UltraScale Architecture SelectIO Resources (UG571)

The transceiver REFCLK pins available on MC2 and MC3 have on board AC coupling capacitors. The transceiver data lanes are directly connected to MC3. The carrier board will need to determine whether data lane AC coupling is required for the specific transceiver application.

More information about pin features is available on the pins page.

There are two options for the ADC reference voltage, and one of them must be implemented in your design for proper operation of the ADC. The Artix UltraScale+ provides an internal ADC reference voltage, or an external precision reference can be provided for optimal performance of the ADC. See AMD UG580 UltraScale Architecture System Monitor for additional details.

To enable the internal ADC reference voltage the VREFP pin available on MC2 should be shorted to the GNDADC pin.

To provide a precision ADC reference voltage connect an external reference voltage to the VREFP pin available on MC2. An example of this design can be found in the BRK8305 design.

More information can be found in the SYSMON section of the Expansion Connectors page.

By default the VBATT functionality is disabled by the 0-Ω resistor R2 connecting it to ground. If it is required in your design, R2 must be removed. Then VBATT can be accessed on MC2.

If your design uses an input signal standard that requires an externally provided voltage reference, the VREF pin for Bank 64 (HP) is available on MC1. Using an external VREF requires removing a resistor and placing a capacitor in its place. More information can be found in the Reference Voltage Pins section of the Expansion Connectors page.

A JTAG connection is available on MC2 that may be used in your design. A JTAG connector must be added to your design if JTAG access to the FPGA is required. For more information see the Expansion Connectors page.

Refer to the XEM8305 mating board diagram for placement locations of the EdgeRate connectors and mounting holes. This diagram can be found on the Specifications page of the XEM8305 documentation.

Refer to the XEM8305 Specifications for a comprehensive mechanical drawing. Also refer to the BRK8305 as a reference platform. The BRK8305 design files can be found in the Downloads section of the Pins website (login required).

For recommended PCB footprint of the ERF6 connectors, refer to the footprint drawings provided by Samtec (ERF6 product page). Find the connector part numbers on the Expansion Connectors page.

Refer to the XEM8305 Specifications for a comprehensive mechanical drawing. Also refer to the BRK8305 as a reference platform. The BRK8305 design files can be found in the Downloads section of the Pins website (login required).

Refer to the XEM8305 mechanical drawing for locations of the USB-C connector. This drawing is available on the Specifications page of the XEM8305 documentation.

Thermal dissipation for the XEM8305 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

An active FPGA cooling solution is recommended for any design with high power consumption. Opal Kelly provides an optional fansink designed to clip onto the FPGA, however the XEM8305 does not have the power connector for the fan onboard. The fan power must be supplied from the carrier board. See the Specifications page for more information. Some designs may require a different cooling solution. Thermal analysis and simulation may be required.