The XEM6010 requires that this supply be clean, filtered, and within the range of 4.5v to 5.5v. This supply must be delivered through the +VDC pins on the two device’s two expansion connectors or the DC power connector..
The expansion bus has several power supply pins, described below:
• +VDC is provided by an external device to the XEM6010. It must be a clean, filtered supply within the range of +4.5 volts and +5.5 volts.
• +3.3v is the output of a 2-Amp switching regulator on the XEM6010.
• +1.8v is the output of a 2-Amp switching regulator on the XEM6010.
• +1.2v is the output of a 2-Amp switching regulator on the XEM6010.
• +VCCO0 is the bank-0 I/O voltage to the FPGA. Factory default is +3.3v
• +VCCO1 is the bank-1 I/O voltage to the FPGA. Factory default is +3.3v
The XEM6010 is designed to be operated from a 5-volt power source supplied through the DC power jack on the device or the expansion connectors on the bottom of the device. This provides power for the three high-efficiency switching regulators on-board to provide 3.3v, 1.8v and 1.2v. 0.9v is derived from the 3.3-volt supply using a small low-dropout (LDO) regulator for use as a DDR2 termination voltage. Each of the three switching regulators can provide up to 2A of current.
DC Power Connector
The DC power connector on the XEM6010 is part number PJ-102AH from CUI, Inc. It is a standard “canon-style” 2.1mm / 5.5mm jack. The outer ring is connected to DGND. The center pin is connected to +VDC.
The table below can help you determine your power budget for each supply rail on the XEM6010. All values are highly dependent on the application, speed, usage, and so on. Entries we have made are based on typical values presented in component datasheets or approximations based on Xilinx power estimator results. Shaded boxes represent unconnected rails to a particular component. Empty boxes represent data that the user must provide based on power estimates.
The user may also need to adjust parameters we have already estimated (such as FPGA Vcco values) where appropriate.
|USB 2.0, PLL||320 mW|
|DDR2||600 mW||250 mW|
|FPGA Vccaux||250 mW|
|FPGA Vcco3 (DDR2), est.||250 mW|
|FPGA Vcco2 (USB), est.||250 mW|
|Available||2,400 mW||3,600 mW||6,600 mW|
Example XEM6010-LX150 FPGA Power Consumption
XPower Estimator version 12.3 was used to compute the following power estimates for the Vccint supply. These are simply estimates; your design requirements may vary considerably. The numbers below indicate approximately 70% to 80% utilization.
|Clock||150 MHz GCLK – 70,000 fanout||384 mW|
|Clock||100 MHz GCLK – 70,000 fanout||256 mW|
|Logic (DFF)||150 MHz, 70,000 DFFs||380 mW|
|Logic (DFF)||100 MHz, 70,000 DFFs||232 mW|
|Logic (LUT)||150 MHz, 32,000 Combinatorial, 1,000 SR, 1,000 RAM||287 mW|
|Logic (LUT)||100 MHz, 32,000 Combinatorial, 1,000 SR, 1,000 RAM||191 mW|
|BRAM||18-bit, 100 @ 150 MHz, 100 @ 100 MHz||237 mW|
|DSP||150 MHz, 140 slices||78 mW|
|MCB||150 MHz||85 mW|
|Misc.||DCM, PLL, etc.||100 mW|