The Micron DDR2 SDRAM is connected exclusively to the 1.8-v I/O on Bank 3 of the FPGA.  The tables below list these connections.

The DDR2 clocking is designed to be source-synchronous from the FPGA.  This means that the FPGA sends the clock signal directly to the SDRAM along with control and data signals, allowing very good synchronization between clock and data.

Spartan-6 has integrated memory control blocks to communicate with the external DDR2 memory on the XEM6010.  This is instantiated using the Xilinx Core Generator (memory interface generator, or MIG) to create a suitable memory controller for your design.  You should read and become familiar with the DDR2 SDRAM datasheet as well as MIG and the core datasheet.  Although MIG can save a tremendous amount of development time, understanding all this information is critical to building a working DDR2 memory interface.

The XEM6010 provides 1.2v as Vccint.  According to the memory controller block documentation, the Spartan-6, -2 speed grade can operate memory to 312.5 MHz with this internal voltage.

The following are the settings used to generate the MIG core for our RAMTester sample using Xilinx Core Generator.  These settings were used with ISE 12.2 and MIG 2.3.  Note that settings may be slightly different for different versions of ISE or MIG.