Three high-density connectors are available on the bottom-side of the XEM8305 PCB. These expansion connectors provide user access to several power rails on the XEM8305, the JTAG and SYSMON interfaces on the FPGA, 124 I/O pins, and access to the GTH transceiver banks.

The table below lists the Samtec connector part numbers as well as the mating connector and total mated height:

MC1 is an 100-pin high-density connector providing access to FPGA Banks 64 (HP) and 84 (HD). VCCO_64 and VCCO_84 connections are also available on this connector. An external rail must be provided on the carrier board to power these I/O banks. See the External I/O Voltage section for more details.

DC input power must be connected to MC1 to supply power to the XEM8305.

Pin mappings for MC1 are listed on the pins page. See the Considerations for Differential Signals section below for information on expansion signal routing.

MC2 is an 80-pin high-density connector providing access to FPGA Banks 85 (HD), 86 (HD). VCCO_85 and VCCO_86 connections are also available on this connector. External power rails must be provided on the carrier board for these I/O banks. See the External I/O Voltage section for more details.

JTAG and XADC connections are also available on MC2.

Pin mappings for MC2 are listed on the pins page. See the Considerations for Differential Signals section below for information on expansion signal routing.

MC3 is an 80-pin high-speed connector providing access to GTH transceiver banks 224, 225, and 226. This includes connections to MGTREFCLK0 (224) and MGTREFCLK0 (225). The MGTREFCLK0 (226) connection is available on MC2.

The provided REFCLK pins have on board AC coupling capacitors while the transceiver lanes are directly connected to MC3.

Pin mappings for MC3 are listed on the pins page. See the Considerations for Differential Signals section below for information on expansion signal routing.

* – Note: Voltage ranges specified here are the range supported by the FPGA bank itself, not the range of the power supply connected to the bank. For power supply ranges refer to Device Settings.

** – Note: One bank 64 I/O pin is used for a VRP resistor by default. The resistor can be moved to connect the I/O pin to MC1 instead. See the VRP information below for details.

The Artix UltraScale+ FPGA allows users to set I/O bank voltages in order to support several different I/O signal standards. External power rails must be provided on the carrier board for these I/O banks. See the External I/O Voltage section for more details.

The expansion connectors are use to provide power to the XEM8305, as well as providing the carrier board assess to on board regulators. These power pins are listed on the Pins sheet. Further power details can be found on the Powering the XEM8305 page.

The XEM8305 provides a power good signal on the expansion connector MC1 to signal that all on board power rails are up and good. The XEM8305_PG signal can be used to sequence the power on of external VCCO I/O regulators. FPGA power is good when this signal is high with a 1.8V signal level.

Available global clock input fabric pins are shown in the XEM8305 Pins Reference. You can use the filter options to display these pins.

MGT Refclock 0 inputs are available on the expansion connector for all 3 transceiver quads (224, 225 and 226).

The JTAG connections on the FPGA are wired directly to the expansion connector MC2 with 4.7kΩ pull-up resistors on TDI, TCK and TMS. The JTAG signal voltage is 1.8V. An appropriate connector (such as a 2mm connector compatible with the JTAG cable) is need on the attached peripheral to the XEM8305. Our BRK8305 has this connector and may be used as a reference.

FPGA system monitor signals are are wired directly to the expansion connector MC2.

VREFP may optionally provide a precision reference for optimal performance of the ADC. See UG580 UltraScale Architecture System Monitor for additional details.

By default, C168 is populated with a 0.1-μF decoupling capacitor so that an external voltage reference may be used. To enable the internal reference instead, the carrier board must short VREFP (MC2 pin 14) to GNDADC (MC2 pin 16). Alternatively, C168 could be replace with a 0-Ω 0402 resistor.

VREFN (FPGA P13) is connected directly to GNDADC.

The Artix UltraScale+ XADC feature is routed through two 100Ω resistors to the MC2 connector. There is a 2.2 n capacitor installed across the two FPGA pins for decoupling.

By default the VBATT functionality is disabled by the 0-Ω resistor R2 connecting it to ground. If it is required in your design, R2 must be removed. Then VBATT can be accessed on MC1.

The Artix UltraScale+ supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM8305 supports these Vref applications on bank 64 (HP). See AMD documentation UG912 and UG571 for more information on using Vref.

For Bank 64, the Vref pin is routed to expansion connector MC1. By default the Vref pin is pulled to ground with a 1k resistor. This supports usage of the internal Vref, or no Vref. If an external Vref is required for your application, the resistor can be removed and a 0.022 µF – 0.47 µF capacitor can be placed in position R64 to decouple the Vref pin.

By default the XEM8305 connects the multi-purpose VRP pin on bank 64 (HP) to ground via a 240 Ohm resistor. This supports certain IOSTANDARD‘s like MIPI on bank 64. If such IOSTANDARD‘s are not required, the 240 Ohm resistor (R159) can be removed, and a 0 Ohm resistor placed on R158 to connect this I/O pin to the MC1 expansion connector on pin 87. In the Pins sheet this extra I/O is labeled as RESERVED1.

Please see the UltraScale Architecture SelectIO Resources for more details about the VRP pin and IOSTANDARD support.

The XEM8305 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs. Please refer to the Artix UltraScale+ datasheet for details on using differential I/O standards with the Artix UltraScale+ FPGA.

In order to use differential I/O standards with the Artix UltraScale+, you must set the VCCO voltages for the appropriate banks according to the Artix UltraScale+ datasheet.

HD banks only support LVDS inputs, and only with external termination. The XEM8305 provides optional external termination resistor positions under the FPGA. As such termination would interfere with the I/O being used as single ended connections, these termination resistors are not populated by default. See the table below to find the termination resistor designator for each HD bank differential pair. The resistor designators are marked on the PCB silkscreen. 100 Ohm resistors can be placed as external termination for each pair.

HP banks support LVDS inputs and outputs. The bank VCCO must be set to 1.8V to use LVDS outputs. This also allows the use of the available internal termination on LVDS inputs.

Please see LVDS Interface Checklist for more information. Also see DS931 for information regarding the LVDS DC Specifications on the Artix UltraScale+.

Single-ended fabric I/O are routed to the expansion connectors with 50Ω characteristic impedance. Differential fabric I/O and transceiver signals are routed to the expansion connectors as pairs with 100Ω differential impedance.

It is desirable that the route lengths of a differential pair be matched within some specification. Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors, and the length of all pairs is matched to within 5 mils (including pin/package delays). Individual PCB routing lengths for all expansion connections are available on the XEM8305 Pins Reference page. The lengths published there represent routed PCB lengths only and do not include the pin/package delays. Pin/package delay information may be obtained from the AMD design tools.

Artix UltraScale+ FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the XEM8305 holds the PUDC_B pin high with a 1kΩ resistor at R125, disabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 1kΩ resistor at R128 and removing the 1kΩ resistor at R125, pulling the PUDC_B pin to ground.