This reference is provided to help guide you through the design process of a mating peripheral to the ZEM5310. It is not intended to be a comprehensive instruction manual. While we put forth great effort to reduce the effort required to build an FPGA-enabled platform, there are hundreds of pages of product documentation from Intel that should be considered. Use this guide as a roadmap and starting point for your design effort.

• ZEM5310 Specifications
• BRK5310 Breakout Board
• Samtec BTE product page
• Samtec BTE data sheet
• Intel Power Estimator

Input power to the ZEM5310 may be applied either through the DC barrel jack or through mezzanine header MC1. For information on the barrel jack dimensions and polarity, see Powering the ZEM5310. For information on mezzanine header pin assignments, see the ZEM5310 Pins Reference.

The total operating power budget is an important system consideration. The power budget for the ZEM5310 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design.

The onboard ZEM5310 power supply regulators provide power for all on-board systems, including the VCCIO rails provided to the mezzanine headers. The Power Budget table on the Powering the ZEM5310 page indicates the total current available for each supply rail. This table may be used to estimate the total amount of input power required for your design.

Details on the available standards can be found in the following Intel documentation:

• Cyclone V Device Datasheet (CV-51002)
• Cyclone V Device Handbook Volume 1: Device Interfaces and Integration (CV-5V2)

Voltage supply rails VCCO_MC1 and VCCO_MC2 power the FPGA I/O banks on mezzanine connectors MC1 and MC2, respectively. By default, these rails are powered by an on-board 2.5V regulator. Power to these rails may also be user-supplied through the mezzanine connectors – this requires removal of ferrite beads on the ZEM5310 and connection of power to the appropriate pins on the connectors. More information can be found on the Expansion Connectors page. See the ZEM5310 Pins Reference for details about FPGA bank power assignments.

Refer to the ZEM5310 mating board diagram for placement locations of the mezzanine connectors (Samtec BTE series) and mounting holes. This diagram can be found on the Specifications page of the ZEM5310 documentation.

For recommended PCB layout of the Samtec BTE connector, refer to the BTE footprint drawing.

Refer to the ZEM5310 Specifications for a comprehensive mechanical drawing. Also refer to the BRK5310 as a reference platform. The BRK5310 design files can be found in the Downloads section of the Pins website.

Refer to the ZEM5310 mechanical drawing for locations of the USB jacks and the DC power jack. This drawing is available on the Specifications page of the ZEM5310 documentation.

Thermal dissipation for the ZEM5310 is highly dependent on the FPGA’s operating parameters and this can only be determined in the context of an actual target design. The type of FPGA cooling solution required for your design should be determined through thermal analysis and simulation as required.

The Samtec BSE-series connectors on the ZEM5310 mate with BTE-series connectors on the carrier board. The BTE series is available in several stacking height options from 5 to 30 mm. The stack height is determined by the “lead style” of the BTE connector.

Note that increased stack height can lead to decreased high-speed channel performance. Information on 3-dB insertion loss point is available on the Samtec website.