Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (QSF, SDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM6001 may be found at the link to the right. 

Three 0.1”-spaced expansion connectors (JP1, JP2, JP3) are available to connect the module to your devices.  These connectors provide 3.3v power, ground, PLL outputs, and 90 FPGA pins for general I/O.  Of the 90 FPGA pins, 13 are FPGA GCLK pins which can be used for global clock inputs to the fabric.  All expansion connectors are on a 0.1” grid so that the entire module can piggy-back onto a standard 0.1” PCB protoboard.

NOTE: The expansion connectors are not installed at the factory to provide you the flexibility of installing your choice of expansion — directly soldering wires, or using stacking or right-angle connectors.

JP1 is a 20-pin dual-row 100-mil header, four pins of which are dedicated to power supply.  The other 16 pins connect directly to the Spartan 6 on bank 1.  Pins 17 and 18 of the header connect to global clock pins on the FPGA and can therefore be used as clock inputs to the internal clock network.  All 16 FPGA pins may be used as general-purpose input/output.

JP2 is a 50-pin dual-row 100-mil header providing access to FPGA bank 3.  Several pins of this header are dedicated to power supply (+3.3VDD and DGND).  Pin 4 of this header is connected to a global clock input on the FPGA and can therefore be used as an input to the global clock network.

Pin 3 on this header is SYSCLK5 and is directly connected to LCLK5 (pin 14) on the Cypress CY22150 PLL.  Using FrontPanel’s PLL Configuration Dialog, you can configure the clock signal present on this pin.

JP3 is a 50-pin dual-row 100-mil header providing access to FPGA bank 1.  Several pins of this header are dedicated to power supply (+3.3VDD and DGND).  Pin 47 of this header is connected to a global clock input on the FPGA and can therefore be used as an input to the global clock network.

Pin 48 on this header is SYSCLK4 and is directly connected to LCLK4 (pin 12) on the Cypress CY22150 PLL.  Using FrontPanel’s PLL Configuration Dialog, you can configure the clock signal present on this pin.

JP4 is the 14-pin 2-mm JTAG connector on-board and is connected only to the FPGA.  The connector pinout is compatible with the Xilinx JTAG cable for JTAG configuration and ChipScope.  The JP4 pins are connected as shown below: