There are 27 pins that connect the on-board USB microcontroller to the FPGA.  These pins comprise the host interface on the FPGA and are used for configuration downloads.  After configuration, these pins are used to allow FrontPanel communication with the FPGA.

If the FrontPanel okHostInterface module is instantiated in your design, you must map the interface pins to specific pin locations using Xilinx LOC constraints.  This may be done using the Xilinx constraints editor or specifying the constraints manually in a text file.

A template constraints file (xem6001.ucf) is located in the Samples directory of the FrontPanel installation.  This file lists all the XEM6001 pins and maps them to the appropriate FPGA pins using LOC (location) constraints.  You can use this template to quickly get the pin locations correct on a new design.

MUXSEL is a signal on the XEM6001 which selects the signal path to the FPGA programming signals D0 and CCLK.  When low (deasserted), the FPGA and USB microcontroller are connected.  When high (asserted), the FPGA and Flash are connected.

In normal USB-programmed operation, JP5 is positioned at “USB” and pulls MUXSEL low, connecting the FPGA and USB microcontroller at all times.  This allows USB-based programming of the FPGA and subsequent USB communication with the FPGA design after configuration.

In order to allow the Flash to configure the FPGA, JP5 is positioned at “PROM.”  In order to deassert MUXSEL post-configuration, your design must deassert MUXSEL.  This allows the FPGA design to properly startup and allows for communication over USB even after the Flash has configured it.

The end result is that your FPGA design should always tie HI_MUXSEL to 0.  This is the case regardless of how the design was configured (via Flash or USB).  For example, in Verilog: 

assign hi_muxsel = 1'b0;