Unlike our integration modules, breakout boards are not intended for production integration. We reserve the right to change dimensions and functionality of this board at any time and may not necessarily have the previous version available for purchase.

Powering the BRK8350

The BRK8350 requires a clean, filtered, DC supply within the range of 6 V to 16 V. This supply may be delivered through the DC power connector (rated to 5 A max current) on the BRK8350 itself or the DC power connector on the XEM8350. Please refer to Powering the XEM8350 for information on the XEM8350 power systems.

Peripherals and Connectors

The table below summarizes the various connectors on the BRK8350. The XEM8350 Pin List has connection information in the "BRK8350" column. Additionally, please refer to the schematics and layout available online for detailed connection diagrams.

Connector TypeRefDesFPGA Bank
SYZYGY StandardJ148
SYZYGY StandardJ247
SYZYGY StandardJ428
SYZYGY StandardJ524
SYZYGY Transceiver (TXR-4)J8GTH 226
SYZYGY Transceiver (TXR-4)J23GTH 225
U.FLJ15-16, J19-20GTH 126
SMAJ6-7, J9-14GTH 128
SATAJ26-27GTH 128
M.2J32GTH 127

100-MHz Oscillator

The 100-MHz oscillator is provided as an alternate external reference for transceivers.

SFP Transceiver Sockets

The BRK8350 has two QSFP cages installed, but the optical transceivers are optional. The following Finisar part is one example option.

ManufacturerPart NumberDigi-Key P/NApproximate Cost
FormericaTQS-Q14H9-J831785-1074-ND$212.80 / each

M.2 Socket

The M.2 connector (J32) is an M-keyed Socket 3 interface which supports SATA and PCIe-based SSD applications. The connector fits 22-mm wide modules. A positionable standoff is included for secure mounting of module types 2230, 2242, 2260, and 2280.

An on-board 100-MHz MEMS oscillator provides the reference clock to the M.2 connector (pins 53/55).

SYZYGY Compatibility Table (PCB Revision Exx)


PCB Revision Exx

The GTH RX lanes on connectors QSFP1 and QSFP2 are connected in the reverse order of the GTH TX lanes between expansion connector MC3 and the QSFP1 and QSFP2 connectors. RX Lane 1 of each connector is connected to RX Lane 4 of the corresponding GTH quad, TX Lane 1 of each connector is connected to TX Lane 1 of the corresponding GTH quad. This can result in problems with some protocols that require that each lane be connected in order for both RX and TX. This can also result in issues when channels within the quad are used individually, as the RX and TX lanes will be connected to separate channels. This will be resolved in the next revision of the BRK8350 PCB, this is tracked as ECR-10076.