The SZG-PMOD4 is a SYZYGY Standard module that provides expansion to up to four Digilent Pmod peripherals.


Resources

SYZYGY Information

Compatibility Table

Compatibility ParameterSpecification
Port typeSYZYGY Standard
WidthSingle
5V supply requiredNo
Nominal 5V supply currentN/A
Nominal 3.3V supply currentDepends on Pmod peripherals
VIO supply voltage3.3V
Nominal VIO supply currentDepends on Pmod peripherals
Total number of I/O24
Number of differential I/O pairs0

DNA Data

This data is stored in the SYZYGY DNA microcontroller on the SZG-PMOD peripheral.

Note that the maximum 3.3V load below is an overestimate to account for the potential variability in current loads between Pmod modules.

DNA ParameterData
Max 5V Load0 mA
Max 3.3V Load1000 mA
Max VIO Load0 mA
IS_LVDSFalse
IS_DOUBLEWIDEFalse
VIO Min3.3V
VIO Max3.3V


Design

The PMOD4 peripheral is a basic device that breaks out a single SYZYGY Standard port into up to 4 Digilent Pmod connectors.

Each signal is routed through a 200Ω series resistor before connecting to its corresponding SYZYGY connector pin. This is to reduce current in the case of a shorted connection to avoid damage to the FPGA I/O.

Additionally, each signal is routed through an ESD protection diode (ON Semiconductor NSQA6V8AW5T2G) on the Pmod side of the series resistor.

POD1 Connections

PMOD I/OSYZYGYJ1 Pin
1S1520
2S1318
3S1116
4S914
5DGND
6+3.3VDD
7S1419
8S1217
9S1015
10S813
11DGND
12+3.3VDD


POD2 Connections

PMOD I/OSYZYGYConnection
1S22J1-27
2S20J1-25
3S18J1-23
4S16J1-21
5DGND
6+3.3VDD
7S23J1-28
8S21J1-26
9S19J1-24
10S17J1-22
11DGND
12+3.3VDD


POD3 Connections

PMOD I/OSYZYGYConnection
1S7J1-12
2S5J1-10
3S3J1-8
4S1J1-6
5DGND
6+3.3VDD
7S6J1-11
8S4J1-9
9S2J1-7
10S0J1-5
11DGND
12+3.3VDD


POD4 Connections

PMOD I/OSYZYGYConnection
1C2P_CLKnJ1-36
2C2P_CLKpJ1-34
3S27J1-32
4S25J1-30
5DGND
6+3.3VDD
7P2C_CLKnJ1-35
8P2C_CLKpJ1-33
9S26J1-31
10S24J1-29
11DGND
12+3.3VDD


Product Lifecycle

PCB Revision History

Date CodeDetail
20170719First production PCB.

Known Issues

VIO Back Powering

SZG-PMOD4 boards with PCB date code 20170719 are designed such that the 3.3V rail powers all Pmod peripherals connected to the SZG-PMOD4. It is possible for Pmod peripherals to back power the VIO rail through FPGA I/O internal clamp diodes under the following conditions:

  • +3.3V power is enabled while +VIO is disabled. The SYZYGY specification calls for +3.3V to turn on first. The carrier implementation and peripheral configuration determines how long this condition lasts. It could be short (10's of milliseconds) or it could be indefinite (if VIO is never enabled).
  • The peripheral drives (applies) a voltage onto the I/O pins.

The scope of the issue depends on the specific carrier and peripherals in an application. Damage can occur to the FPGA is the back current applied to the pin exceeds 10mA. On the Opal Kelly XEM7320, there are no other significant power users attached to the VIO and no VIO is shared among peripherals. Therefore, no significant current would pass through the clamp diodes. On the Opal Kelly Brain-1, a second peripheral on the same VIO bank could draw current and force this current through the clamp diodes. Other carrier designs may also experience damage if their VIO power supply design is capable of sinking current prior to the VIO rail powering on.

A revised design to resolve this issue is in progress. At this time, we do not feel that this presents a significant risk of damage for most system configurations.

If you have any questions or comments, please feel free to reach out to Opal Kelly Support.