Configuration Parameters

This technical reference covers both the FrontPanel Subsystem and LEDs Vivado IP cores. The IP Cores’ configuration parameters are used when generating the IP Cores’ output products. The IP Cores’ parameters are validated to ensure they conform to the requirements laid out in their respective tables (Table 1.0 and Table 1.1).

Setting Parameters Through TCL:

The parameters can be set through TCL using the following command structure:

set_property -dict [list CONFIG.<Param Name> {<value>} <Additional Param/value pairs>] [get_ips <IP Instance>]
Code language: HTML, XML (xml)

For example:

set_property -dict [list CONFIG.BOARD {XEM8320-AU25P} CONFIG.WI.COUNT {1} CONFIG.WI.ADDR_0 {0x08}] [get_ips frontpanel_example]
Code language: CSS (css)

Dual Host Interface Configuration Parameters:

Currently, the XEM8350 is the only device to support a secondary Host Interface. Devices supporting the secondary Host Interface provide additional parameters by prepending an “S” field onto their counterparts laid out in Table 1.0. These parameters have identical functionality and the same validation/conformity rules as their counterparts. For brevity, these parameters are removed from Table 1.0:

  • S.<type>.COUNT
  • S.<type>.ADDR_<31-0>
  • S.RB.EN

Additionally, S.EN is used to enable the secondary host interface and is listed in Table 1.0.

Reference Tables

The parameters are categorized into the Types defined below:

User Intended for user configuration
GUI Intended to be used in the GUI discovery workflow. Not relevant beyond the discovery stage when utilizing TCL configuration
InternalDo not manually set

FrontPanel Subsystem IP Core Parameters

Param NameDescriptionRangeTypeSupported BoardsNotes
BOARDSelects target boardTable 3.3UserAllTable 3.3
DNA.ENDNA port enablementfalse/trueUserAll
WI.COUNTNumber of WireIn Endpoints[0, 32]UserAll(1)
WO.COUNTNumber of WireOut Endpoints[0, 32]UserAll(1)
TI.COUNTNumber of TriggerIn Endpoints[0, 32]UserAll(1)
TO.COUNTNumber of TriggerOut Endpoints[0, 32]UserAll(1)
PI.COUNTNumber of PipeIn Endpoints[0, 32]UserAll(1)(2)
BTPI.COUNTNumber of Block Throttled PipeIn Endpoints[0, 32]UserAll(1)(2)
PO.COUNTNumber of WireIn Endpoints[0, 32]UserAll(1)(3)
BTPO.COUNTNumber of Block Throttled PipeOut Endpoints[0, 32]UserAll(1)(3)
RB.ENRegister Bridge enablementfalse/trueUserAll
WI.ADDR_<31-0>32 Address Bins for Endpoint[0x00, 0x1f]UserAll(4)(5)
WO. ADDR_<31-0>32 Address Bins for Endpoint[0x20, 0x3f]UserAll(4)(5)
TI. ADDR_<31-0>32 Address Bins for Endpoint[0x40, 0x5f]UserAll(4)(5)
TO. ADDR_<31-0>32 Address Bins for Endpoint[0x60, 0x7f]UserAll(4)(5)
PI.ADDR_<31-0>32 Address Bins for Endpoint[0x80, 0x9f]UserAll(4)(5)
BTPI.ADDR_<31-0>32 Address Bins for Endpoint[0x80, 0x9f]UserAll(4)(5)
PO.ADDR_<31-0>32 Address Bins for Endpoint[0xa0, 0xbf]UserAll(4)(5)
BTPO. ADDR_<31-0>32 Address Bins for Endpoint[0xa0, 0xbf]UserAll(4)(5)
BITSTREAM.FLASHFlash configuration enablementfalse/trueUserXEM8320-AU25P, XEM8310-AU25P, XEM8350-KU060(6)
CONFIG.S.ENSecondary Host Interface enablementfalse/trueUserXEM8350-KU060
EXDES.FLOWExample Design workflow categoryNot RelevantGUIAll(7)
EXDES. SELECTIONChoice from available Example DesignsNot RelevantGUIAll(7)
GUI.APPLY_PRESETTrigger param used in applying presets within the GUI[1, ∞)GUIAll(7)
DNA.WIDTHDNA width variable used in internal generation. Automatically set based on BOARD param7 Series – 57
UltraScale – 96
Table 3.1 FrontPanel Subsystem IP Core Parameters


  1. The included address bins start at <type>.ADDR_0 through to the <type>.COUNT specified, i.e., a <type>.COUNT of 3 will generate endpoints for the addresses in bins <type>.ADDR_0 through <type>.ADDR_2.
  2. PI & BTPI Endpoint types share the same address space. Their summed COUNTs cannot exceed 32, i.e. PI.COUNT + BTPI.COUNT ≤ 32.
  3. PO & BTPO Endpoint types share the same address space. Their summed COUNTs cannot exceed 32, i.e. PO.COUNT + BTPO.COUNT ≤ 32.
  4. Addresses must be in HEX format, i.e., 0x04
  5. No two Endpoint address bins can have the same address.
  6. Only supported on boards with FPGA Flash.
  7. Not intended outside of the GUI flow.
  8. Does NOT provide utility in applying board interface constraints as seen in Xilinx provided IP Cores. IP Core automatically applies board constraints through other means.
  9. Internal Parameter is automatically configured appropriately based on User parameter types.

LEDs IP Core Parameters

Param NameDescriptionRangeTypeSupported BoardsNotes
BOARDSelects target boardTable 3.3UserAllTable 3.3
IOSTANDARDSelects IOSTANDARD constraint to apply to LEDsLVCMOS12, LVCMOS15, LVCMOS18UserXEM8320-AU25P, XEM8350-KU060(1)
WIDTHNumber of onboard LEDsVariableInternalAll
DRIVERTYPEDetermines which LED driver logic to generatestandard, inverted, tristateInternalAll
Table 3.2 LEDs IP Core Parameters


  1. Used for boards whose LEDs are connected to a variable bank voltage controlled by VIO.

IP Cores’ Enforced FPGA Parts

IP Cores` supported Opal Kelly BoardsIP Cores` enforced FPGA Part
Table 3.3 Enforced FPGA parts