ZYNQMP Processing System

The hard processor system (PS) on the Zynq 7 requires configuration to understand how to interact with the peripherals on the ECM1900. At boot, this configuration is entered into registers on the CPU through the FSBL or U-Boot SPL. Any changes made to this configuration will require generating a new hardware handoff (hdf) file along with a re-build of the U-Boot SPL or FSBL.

The configuration parameters below correspond to the configuration for the reference design provided by Opal Kelly. Applications conforming to the settings outlined below will be compatible with the reference designs and official Linux image from Opal Kelly. Other designs may require some changes to the parameters listed below, resulting in incompatibilities with the Opal Kelly U-Boot and Linux configuration.

PS-PL Configuration

PARAMETERECM1900
General 
Fabric Reset Enable Disabled
All other settingsDefault/Disabled
HP Master AXI Interface 
AXI HPM0 LPDDisabled
All other settingsDefault/Disabled

Peripheral I/O Pins

MIO PIN (RANGE)ASSIGNMENT
MIO 0-13GPIO0
MIO 14-15UART0
MIO 16-17I2C1
MIO 18-25GPIO0
MIO 26-37GPIO1
MIO 38USB0 Reset
MIO 39-42SD1
MIO 43-44GPIO1
MIO 45SD1 Card Detect
MIO 46-51SD1
MIO 52-63USB0
MIO 64-77GPIO2

MIO Configuration

This majority of this section is configured correctly according to the settings entered in the Peripheral I/O Pins section.

Bank 0-3 on the ECM1900 runs at 1.8V (LVCMOS18). The default for these banks is LVCMOS33.

The following changes should be made:

I/O PERIPHERALS 
SD 1 
CDMIO 45
USB ResetSeparate MIO Pin
USB0MIO 38

Clock Configuration

(*This information is not verified) The PS receives a 50 MHz input clock. The reference design configures the CPU Clock Ratio to 6:2:1.

All values can be set at default, except:

COMPONENTCLOCK SOURCEREQUESTED FREQUENCY (MHZ)
Processor/Memory Clocks  
ACPUARM PLL(APLL)1200
DDRDDR PLL(DPLL)600

DDR Configuration

(see the DDR4 Memory page)

Interrupts

All Fabric Interrupts are disabled by default in the reference design.