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Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (QSF, SDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the ZEM5305 may be found at the link to the right. 

Mezzanine Connectors (MC1 and MC2)

MC1 contains most of the system power supply pins in addition to 48 FPGA I/O connections. Please see the ZEM5305 Pins Reference for details.

  • +5VUSB from the USB connector
  • +3.3VDD, +2.5VDD, +1.5VDD, +1.2VDD, and +1.1VDD system supplies
  • VCCPD2
  • VCCIO4, VCCPD4, and VREF4
  • VCCPD5

MC2 contains the JTAG pins, some I/O power supply pins, and 46 FPGA I/O connections.

FPGA BankPins on MC1Pins on MC2TotalPower Supplies
Bank 2A01616VCCIO2 (MC2-42)
VCCPD2 (MC1-13)
VREF2 (MC2-4) 
Bank 4A47047VCCIO4 (MC1-16)
VCCPD4 (Fixed at +2.5 V)
VREF4 (MC1-18) 
Bank 5A01515VCCIO5 (MC2-41)
VCCPD5 (MC1-17)
VREF5 (MC1-3) 
Bank 5B11516

Clock Pins

The Altera Cyclone V E design establishes several pins that offer dedicated access to the on-chip clock PLL inputs and outputs. These pins are shared with I/O and other functionality, but may have some limitations or restrictions. Please review Altera's Cyclone V documentation to understand how these limitations may affect your design.

Bank / Group (I/O voltage)ZEM5305-A2
CLKINp, CLKINnMC2-75, MC2-77

Considerations for Differential Signals

The ZEM5305 PCB layout and routing has been designed with several applications in mind but, due primarily to space limitations, pair routing has not been performed. The board should still operate over a broad range of frequencies for differential standards, but may require some length matching on the peripheral for best performance. Routed lengths on the ZEM5305 PCB for routes to the expansion connector are listed in the Pins reference.

Characteristic Impedance

The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.

I/O Voltage Pins (VCCIO, VCCPD, and Vref)

Please see the section Powering the ZEM5305 for details on providing the necessary power for the I/O banks.

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