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The DDR3 SDRAM is connected to the 1.5-V I/O on Bank 7A and 8A of the FPGA. The tables below list these connections.

DDR3 PinFPGA Pin

RESET

B22

CK

J9

CK#

J8

CKE

B15

CS#

H8

RAS#

A9

CAS#

A10

WE#

E6

DQS0

H9

DQS0#

G8

DQS1

G12

DQS1#

H12

DM0

A15

DM1

C19

ODT

A13

DDR3 PinFPGA Pin

A0

C11

A1

B11

A2

A8

A3

A7

A4

D11

A5

E11

A6

F8

A7

E7

A8

D9

A9

D8

A10

B6

A11

B5

A12

C8

A13

B8

A14

H6

BA0

C6

BA1

C10

BA2

C9

DDR3 PinFPGA Pin

D0

F12

D1

E12

D2

B12

D3

B13

D4

C13

D5

D13

D6

C14

D7

A14

D8

E14

D9

F15

D10

B18

D11

A17

D12

C15

D13

C16

D14

B16

D15

C18

DDR3 SDRAM Controller Settings

Cyclone V devices support external, high-performance memory through the use of the DDR3 SDRAM Controller with UniPHY provided by Altera. This provides a custom memory controller using the hard memory controller IP present on the Cyclone V devices. These parameters have been used successfully within Opal Kelly but your design needs may require deviations.

Parameters in Bold are those that need to be changed from the default.

All settings are based on Quartus II 15.0.2.

Screenshots of this process are available in the DDR3 Memory Walkthrough.

PHY Settings

SectionParameterZEM5305
 Enable Hard External Memory InterfaceEnabled
General SettingsSpeed Grade8
Clocks

 

Memory Clock Frequency333.3333 MHz

PLL Reference Clock Frequency

100.0 MHz
Rate on Avalon-MM interfaceFull
Enable AFI Half Rate ClockDisabled
Advanced PHY SettingsSupply Voltage1.5V DDR3
PLL Sharing ModeNo Sharing
DLL Sharing ModeNo Sharing
OCT Sharing ModeNo Sharing

Memory Parameters

Select the MICRON MT41K256M16HA-125 memory device preset and click "Apply". This applies all memory parameters correctly with the following exceptions:

SectionParameterZEM5305
 Total Interface Width16
Memory Initialization Options

Output Drive Strength SettingRZQ/6
ODT Rtt Nominal ValueRZQ/6
Auto Selfrefresh MethodAutomatic

Memory Timing

These parameters are set after applying the preset for the Micron memory device above.

Board Settings

The default settings in this tab should be appropriate for the ZEM5305.

Controller Settings

SectionParameterZEM5305
Avalon InterfaceGenerate power-of-2 data bus widths for Qsys or SOPC BuilderDisabled
Generate SOPC Builder Compatible ResetsDisabled
Maximum Avalon-MM Burst Length128
Enable Avalon-MM Byte-enable SignalEnabled
Low Power ModeAll OptionsDisabled
EfficiencyEnable User Auto-Refresh ControlsDisabled
Enable Auto-Precharge ControlDisabled
Local-to-Memory Address MappingCHIP-ROW-BANK-COL
Enable ReorderingEnabled
Starvation Limit for Each Command10 commands
Configuration, Status and Error HandlingAll OptionsDisabled
Multiple Port Front EndExport Bonding InterfaceDisabled
Expand Avalon-MM Data for ECCDisabled
Number of Ports1
Port 0TypeBidirectional
Width128
Priority1
Weight0

Diagnostics

SectionParameterZEM5305
Simulation OptionsAuto-calibration modeSkip calibration
Skip Memory Initialization DelaysEnabled
Enable Verbose Memory Model OutputEnabled
Enable Support for Nios II ModelSim Flow in EclipseDisabled
Debugging OptionsAll OptionsDefault
Efficiency Monitor and Protocol Checker SettingsAll OptionsDefault

DDR3 SDRAM Pin Assignments

After generating the DDR3 controller using the settings above, a set of pin assignments will be created for the memory interface. To apply these settings to a design you must first synthesize the design. Then, from the TCL Scripts tool found in the Quartus Tools menu select the ddr3_interface_p0_pin_assignments.tcl script and select Run. This should apply all required constraints to the design.

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