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Access to eight high-speed serial transceiver pairs (8 Rx and 8 Tx) corresponding to GTX tiles 115 and 116 on the FPGA are available on the expansion connectors. MGTREFCLK0 of tile 115 and MGTREFCLK0 of tile 116 are also routed to expansion connectors. MGTREFCLK1 of tile 115 is connected to a low-jitter 100 MHz LVDS oscillator.

AC-Coupling

0.1μF AC-coupling capacitors are installed between the expansion connectors and the FPGA for all MGTREFCLK signals.

AC-coupling capacitors are not installed for any of the GTP transmit or receive pairs. If AC-coupling is desired or required for the serial application, they should be installed on the peripheral side (your board).

IBERT Configuration

Xilinx provides the IBERT tool to test and experiment with gigabit transceivers.  The settings below are compatible with the XEM7360 using Vivado 2015.1:

Protocol Definition
Silicon VersionGeneral ES / Production
ProtocolCustom 1
Line Rate8 Gbps
Data Width32
Ref Clk100.000 MHz
Quad Count1
Quad PLLChecked
Protocol Selection
GTX LocationQUAD_115QUAD_116
RefClk SelectionMGTREFCLK1_115MGTREFCLK1_116
TXUSRCLK SourceChannel 0Channel 0
Clock Settings
Add RXOUTCLK ProbesUnchecked
Clock TypeSystem Clock
SourceExternal
I/O StandardLVDS
P Package PinAB11
N Package PinAC11
Frequency200 MHz
Enable DIFF Term.Unchecked

Gigabit Transceiver IBERT Performance

Xilinx’s IBERT tool enables an automated self-measurement of a GTP channel’s eye diagram when used in a loopback mode. Eye diagrams for three different speeds were captured using this tool with a simple loopback peripheral attached to the expansion headers. While results may vary, these are typical captures and actually represent the worst case capture over all channels for the respective rates.

Note that in loopback modes, it can be helpful to disable the GBT DFE (decision feedback equalizer) to avoid over-compensation. In these test cases, the DFE has been left enabled.

3.3 Gbps / XEM7360-K160T

6.6 Gbps / XEM7360-K160T

8.0 Gbps / XEM7360-K160T

 

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