Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.
Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.
The Pins reference for the XEM7360 may be found at the link to the right.
Fan Power Supply
A small 2-pin connector (Molex 53398-0271) at JP1 provides power to an optional fan for FPGA cooling. This fan is controlled by a digital fan controller as part of the Device Sensors and Device Settings capabilities. Please see the Device Settings section for details on controlling the fan.
A single FMC-HPC (high pin count) connector provides direct access to I/O pins and Gigabit transceiver on the FPGA. The tables below illustrate the number of pins that are available on an FMC-HPC connector and the number that are routed to available sites on the FPGA.
|HR / HP||Vadj||Voltage Range||MCx|
|Bank 12||HR||Vadj2||0.8-3.3v||MC2||50 (includes MRCC pair)|
|Bank 15||HR||Vadj1||0.8-3.3v||MC1||48 (includes MRCC pair)|
|Bank 16||HR||Vadj1||0.8-3.3v||MC1||48 (includes MRCC pair)|
|Bank 32||HP||Vadj3||0.8-1.8v||MC2||47 (includes MRCC pair)|
|GBT - # of transceivers||8|
Clock Input Pins
Available clock pins are illustrated in the table below. All pins listed are multi-region clock pins.
Setting the Expansion Vadj I/O Voltages
Three programmable high-efficiency switching regulators are on the XEM7360 which control the three adjustable voltages Vadj1, Vadj2, and Vadj3. These are connected to the FPGA bank VCCIO according to the tables above. Please see the Device Settings page for information on configuring these voltages.
For modes that read settings from an IPMI EEPROM on the peripheral, the XEM7360 expects to find this EEPROM at I2C address
The Xilinx Kintex-7 XADC feature is routed through two 1kΩ resistors to the MC2 connector. There is a 0.01 µF capacitor installed across the two FPGA pins for decoupling.
Considerations for Differential Signals
The XEM7360 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs. Please refer to the Xilinx Kintex-7 datasheet for details on using differential I/O standards with the Kintex-7 FPGA.
FPGA I/O Bank Voltages
In order to use differential I/O standards with the Kintex-7, you must set the VCCO voltages for the appropriate banks to 2.5v according to the Xilinx Kintex-7 datasheet. Please see the section above entitled “Setting the FMC Vadj I/O Voltage” for details.
The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.
Differential Pair Lengths
In many cases, it is desirable that the route lengths of a differential pair be matched within some specification. Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.
Reference Voltage Pins (Vref)
The Xilinx Kintex-7 supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM7360 supports these Vref applications for banks 12, 15, 16, and 32. Please see the Xilinx Kintex 7 documentation for more details. In summary,
|FPGA Bank||Vadj||FPGA Pins||MCx Pin||Notes|
|12||Vadj2||W21||MC2:10||The two VREF pins are brought out separately on|
MC2 so they can be used as I/O or VREF.
|15||Vadj1||D16, J20||MC1:114||All four VREF pins of these two banks are connected|
together to a common pin on MC1.
|32||Vadj3||AE16||MC2:114||The two VREF pins are brought out separately on|
MC2. However, AE16 has a 4.7µF capacitor for
I/O State at Power On
Xilinx Kintex-7 FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the XEM7360 holds the PUDC_B pin low with a 1kΩ resistor at R68, enabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 0Ω resistor at R66 and removing the 1kΩ resistor at R68, forcing the PUDC_B pin high.