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Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules. It provides additional information on pin capabilities, pin characteristics, and PCB routing.

Pins can also generate constraint files (XDC) and help you map your HDL net names to FPGA pin locations automatically.

The Pins reference for the XEM7360 may be found at the link to the right. 

Fan Power Supply

A small 2-pin connector (Molex 53398-0271) at JP1 provides power to an optional fan for FPGA cooling. This fan is controlled by a digital fan controller as part of the Device Sensors and Device Settings capabilities. Please see the Device Settings section for details on controlling the fan.

Pin

Signal

1GND
2+5VDC

Mezzanine Connectors

A single FMC-HPC (high pin count) connector provides direct access to I/O pins and Gigabit transceiver on the FPGA. The tables below illustrate the number of pins that are available on an FMC-HPC connector and the number that are routed to available sites on the FPGA.

FPGA Bank

HR / HPVadjVoltage RangeMCx

Count

Bank 12HRVadj20.8-3.3vMC250 (includes MRCC pair)
Bank 15HRVadj10.8-3.3vMC148 (includes MRCC pair)
Bank 16HRVadj10.8-3.3vMC148 (includes MRCC pair)
Bank 32HPVadj30.8-1.8vMC247 (includes MRCC pair)
GBT - # of transceivers    8

Clock Input Pins

Available clock pins are illustrated in the table below. All pins listed are multi-region clock pins.

FPGA Bank

Vadj

FPGA Pins

MCx Pins

Bank 12
MRCC 
Vadj2Y23
AA24
MC2:25
MC2:27 
Bank 15
MRCC 
Vadj1F17
E17
MC1:25
MC1:27
Bank 16
MRCC 
Vadj1E10
D10
MC1:85
MC1:87 
Bank 32
MRCC 
Vadj3AB16
AC16
MC2:85
MC2:87

Setting the Expansion Vadj I/O Voltages

Three programmable high-efficiency switching regulators are on the XEM7360 which control the three adjustable voltages Vadj1, Vadj2, and Vadj3. These are connected to the FPGA bank VCCIO according to the tables above. Please see the Device Settings page for information on configuring these voltages.

For modes that read settings from an IPMI EEPROM on the peripheral, the XEM7360 expects to find this EEPROM at I2C address 0xA2.

XADC

The Xilinx Kintex-7 XADC feature is routed through two 1kΩ resistors to the MC2 connector. There is a 0.01 µF capacitor installed across the two FPGA pins for decoupling.

FPGA Function

FPGA Pin

MC2 Pin

Resistor RefDes

ADC_VN_0P11149R74
ADC_VP_0N12147R73

Considerations for Differential Signals

The XEM7360 PCB layout and routing has been designed with several applications in mind, including applications requiring the use of differential (LVDS) pairs.  Please refer to the Xilinx Kintex-7 datasheet for details on using differential I/O standards with the Kintex-7 FPGA.

FPGA I/O Bank Voltages

In order to use differential I/O standards with the Kintex-7, you must set the VCCO voltages for the appropriate banks to 2.5v according to the Xilinx Kintex-7 datasheet.  Please see the section above entitled “Setting the FMC Vadj I/O Voltage” for details.

Characteristic Impedance

The characteristic impedance of all routes from the FPGA to the expansion connector is approximately 50Ω.

Differential Pair Lengths

In many cases, it is desirable that the route lengths of a differential pair be matched within some specification.  Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible. We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application. Due to space constraints, some pairs are better matched than others.

Reference Voltage Pins (Vref)

The Xilinx Kintex-7 supports both internal and externally-applied input voltage thresholds for some input signal standards. The XEM7360 supports these Vref applications for banks 12, 15, 16, and 32. Please see the Xilinx Kintex 7 documentation for more details. In summary,

FPGA BankVadjFPGA PinsMCx PinNotes
12Vadj2W21MC2:10The two VREF pins are brought out separately on
MC2 so they can be used as I/O or VREF. 
AE21MC2:51
15Vadj1D16, J20MC1:114All four VREF pins of these two banks are connected
together to a common pin on MC1. 
16H11, C13
32Vadj3AE16MC2:114The two VREF pins are brought out separately on
MC2. However, AE16 has a 4.7µF capacitor for
decoupling. 
Y18MC2:70

I/O State at Power On

Xilinx Kintex-7 FPGAs support a weak pull-up state on all I/O pins from power on until first configuration. This behavior is controlled by the PUDC_B pin. By default the XEM7360 holds the PUDC_B pin low with a 1kΩ resistor at R68, enabling the weak pull-up on all I/O pins at power on. This behavior can be changed by inserting a 0Ω resistor at R66 and removing the 1kΩ resistor at R68, forcing the PUDC_B pin high.

 

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