The use of FrontPanel components to control and observe pieces of your FPGA design requires the instantiation of one or more modules in your toplevel HDL. These modules can quickly and easily be added into an existing or new design and take care of all the dirty work of communicating with the FrontPanel software.
The host interface is the block which connects directly to pins on the FPGA which are connected to the USB microcontroller. This is the entry point for FrontPanel into your design.
The endpoints connect to a shared control bus on the host interface. This internal bus is used to shuttle the endpoint connections to and from the host interface. Several endpoints may be connected to this shared bus. FrontPanel uses endpoint addresses to select which endpoint it is communicating with, so each endpoint must have its own unique address to work properly.
FrontPanel supports three basic types of endpoints: Wire, Trigger, and Pipe. Each can either be an input (from host to target) or output (from target to host). Each endpoint type has a certain address range which must be used for proper operation. The address is specified at the instantiation of the endpoint module in your design.
|Wire In||0x00 - 0x1F||Asynchronous||Signal state|
|Wire Out||0x20 - 0x3F||Asynchronous||Signal state|
|Trigger In||0x40 - 0x5F||Synchronous||One-shot|
|Trigger Out||0x60 - 0x7F||Synchronous||One-shot|
|Pipe In||0x80 - 0x9F||Synchronous||Multi-byte transfer|
|Pipe Out||0xA0 - 0xBF||Synchronous||Multi-byte transfer|
Endpoints are instantiated in your HDL design and connected to the okHost target ports. Each endpoint also has one or more ports which are connected to various signals in your design, depending on the endpoint module.
Endpoints attach to the host interface on a shared bus. To properly route signals between the host (PC) and target endpoints, each endpoint must be assigned a unique 8-bit address. For performance reasons (to minimize USB transactions), each endpoint type has been assigned an address range as indicated in the table above. When assigning addresses to your endpoints, be sure to follow these ranges.
The endpoint address is assigned in HDL through an additional 8-bit input port on the endpoint instance. Example instantiation for each endpoint type are shown in the sections below.
Register Bridge (USB 3.0 Only)
FrontPanel for USB 3.0 devices supports Wires, Triggers, and Pipes, as well as an additional Register Bridge endpoint. This register bridge provides a 32-bit address space of 32-bit data words for a total of 16 GB. User HDL responds to read and write requests from this Register Bridge, effectively creating a large synchronous register file.
Endpoint Data Widths
Endpoint data widths vary depending on the interface according to the table below.
|Register Bridge - Address||-||32||-|
|Register Bridge - Data||-||32||-|
Host Interface Clock Speed
The HDL host interface is a slave interface from the host. It runs at a fixed clock rate that is dependent upon the interface type for the device.
- USB 2.0 interfaces run at 48 MHz (20.83 ns clock period)
- USB 3.0 interfaces run at 100.8 MHz (9.92 ns clock period)
- PCI Express (x1) interfaces run at 50 MHz (20 ns clock period)
Building FPGA Projects with FrontPanel HDL Modules
The FrontPanel HDL Modules are provided as pre-synthesized files which get included in your design flow. The following table lists these files and describes its content. By default, these files are installed at
C:\Program Files\Opal Kelly\FrontPanelUSB\FrontPanelHDL. In this directory are several subdirectories that contain HDL modules built for different different devices. Choose the library and NGC files suitable for your device.
Verilog file containing black-box modules for Verilog projects.
VHDL file containing black-box modules for VHDL projects.
Pre-synthesized Xilinx module for the Host.
Pre-synthesized Xilinx module for the Wire In endpoint.
Pre-synthesized Xilinx module for the Wire Out endpoint.
Pre-synthesized Xilinx module for the Trigger In endpoint.
Pre-synthesized Xilinx module for the Trigger Out endpoint.
Pre-synthesized Xilinx module for the Pipe In endpoint.
Pre-synthesized Xilinx module for the Pipe Out endpoint.
Pre-synthesized Xilinx module for the Block-Throttled Pipe In endpoint.
Pre-synthesized Xilinx module for the Block-Throttled Pipe Out endpoint.
The Host Interface is comprised of two components - a core component which is pre-synthesized and a wrapper component (in okLibrary.v or okLibrary.vhd) which includes the core component as well as IOBs required for the connections to FPGA pins.
When you start a new design, you should copy okLibrary.v or okLibrary.vhd into the directory with your other sources and add them to your project. This file will be synthesized just like your other modules except that the HDL is mostly just a placeholder for the modules that have been pre-synthesized. When properly added to a project, Project Navigator will list the source follows similar to what is shown below:
You should also copy the pre-synthesized files (*.ngc) that you use into your project directory. You do not need to copy module files that you are not using. The .ngc files will then be used by the Xilinx tools during the Translate step in order to completely build the FPGA configuration file.